From db630f2030dc303dffe649fdaa999dd581df9edf Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Wed, 17 Jul 2024 20:31:36 -0700
Subject: [PATCH] Update rtl-common, fix some axi violations in cpu writes

---
 hw/super6502_fpga/src/rtl/super_6502_fpga.sv  |  4 +-
 .../src/sub/cpu_wrapper/cpu_wrapper.sv        | 38 +++++++++++++++----
 hw/super6502_fpga/src/sub/rtl-common          |  2 +-
 3 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
index 8616836..175346f 100644
--- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
+++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
@@ -290,6 +290,7 @@ axilxbar #(
 
 axi4_lite_rom #(
     .ROM_SIZE(8),
+    .BASE_ADDRESS(32'h0000ff00),
     .ROM_INIT_FILE("init_hex.mem")
 ) u_rom (
     .i_clk(i_sysclk),
@@ -322,7 +323,8 @@ axi4_lite_rom #(
 );
 
 axi4_lite_ram #(
-    .RAM_SIZE(9)
+    .RAM_SIZE(9),
+    .ZERO_INIT(1)
 ) u_ram(
     .i_clk(i_sysclk),
     .i_rst(~master_resetn),
diff --git a/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv b/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv
index 51958e5..b78a726 100644
--- a/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv
+++ b/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv
@@ -82,6 +82,9 @@ logic w_write_data_en;
 logic [7:0] r_write_data, r_write_data_next;
 logic w_write_data_empty;
 
+logic latched_awvalid, latched_awvalid_next;
+logic latched_wvalid, latched_wvalid_next;
+
 logic [2:0] counter;
 logic w_reset;
 
@@ -160,7 +163,7 @@ always @(posedge i_clk_100 or posedge i_rst) begin
         end else begin
             flag <= '0;
         end
-    end 
+    end
 end
 
 // // This uses inverted clock, remember in sdc?
@@ -204,7 +207,7 @@ always @(posedge i_clk_100 or posedge i_rst) begin
         end else begin
             flag2 <= '0;
         end
-    end 
+    end
 end
 
 localparam MAX_DELAY = 8;
@@ -232,6 +235,9 @@ always_ff @(posedge i_clk_100 or posedge i_rst) begin
         end
 
         rdy_dly <= {rdy_dly[1:0], too_late};
+
+        latched_awvalid <= latched_awvalid_next;
+        latched_wvalid <= latched_wvalid_next;
     end
 end
 
@@ -244,11 +250,11 @@ always_comb begin
     // Set defaults
     o_AWVALID = '0;
     o_AWADDR = '0;
-    o_AWPROT = '0;  
+    o_AWPROT = '0;
     o_WVALID = '0;
     o_WDATA = '0;
-    o_WSTRB = '0;   
-    o_BREADY = '0;  
+    o_WSTRB = '0;
+    o_BREADY = '0;
     o_ARVALID = '0;
     o_ARADDR = '0;
     o_ARPROT = '0;
@@ -259,6 +265,9 @@ always_comb begin
     read_data_next = read_data;
     did_delay_next = did_delay;
 
+    latched_awvalid_next = latched_awvalid;
+    latched_wvalid_next = latched_wvalid;
+
     case (state)
     RESET: begin
         // Is this a CDC violation?
@@ -273,6 +282,8 @@ always_comb begin
         end
 
         did_delay_next = '0;
+        latched_awvalid_next = '0;
+        latched_wvalid_next = '0;
     end
 
     ADDR_CONTROL: begin
@@ -327,9 +338,22 @@ always_comb begin
     end
 
     WRITE_DATA: begin
-        o_AWVALID = '1;
+        if (~latched_awvalid) begin
+            o_AWVALID = i_AWREADY;
+            latched_awvalid_next = '1;
+        end else begin
+            o_AWVALID = '0;
+        end
         o_AWADDR = {r_addr[15:2], 2'b0};
-        o_WVALID = '1;
+
+        if (~latched_wvalid) begin
+            o_WVALID = i_WREADY;
+            latched_wvalid_next = '1;
+        end else begin
+            o_WVALID = '0;
+        end
+
+
         o_WSTRB = 4'b1 << r_addr[1:0];
         o_WDATA = r_write_data << 8*r_addr[1:0];
 
diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common
index 401042b..6bb56be 160000
--- a/hw/super6502_fpga/src/sub/rtl-common
+++ b/hw/super6502_fpga/src/sub/rtl-common
@@ -1 +1 @@
-Subproject commit 401042bb0ff9db0f44dab9cb6e08c71058a1bcb1
+Subproject commit 6bb56be03a32ea76c7477e2403b396ede5818c31