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Fix fpga project config

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Byron Lathi
2023-10-15 21:07:15 -07:00
parent 155e89240a
commit dc2154e2c2
2 changed files with 3 additions and 4 deletions
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4
hw/efinix_fpga/super6502.peri.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sat Jul 22 17:30:06 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" version="2022.2.322" db_version="20231999" last_change_date="Sun Oct 15 21:05:41 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -336,7 +336,7 @@
<efxpt:pll_info>
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_TR1" ref_clock_name="i_sysclk" ref_clock_freq="100.0000" multiplier="16" pre_divider="2" post_divider="4" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clk_50" number="0" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_2" number="1" out_divider="100" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_cpu" number="1" out_divider="100" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
</efxpt:pll>
<efxpt:pll name="pll_sdram_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="8" pre_divider="4" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">

3
hw/efinix_fpga/super6502.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 13:52:14" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 21:06:39" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -9,7 +9,6 @@
<efx:top_module name="super6502"/>
<efx:design_file name="src/super6502.sv" version="default" library="default"/>
<efx:design_file name="src/leds.sv" version="default" library="default"/>
<efx:design_file name="src/addr_decode.sv" version="default" library="default"/>
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default"/>
<efx:design_file name="src/timer.sv" version="default" library="default"/>
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default"/>