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Mega commit to kick things off

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This commit is contained in:
Byron Lathi
2024-09-01 22:23:21 -07:00
parent 8425d6a96e
commit dc90c00172
21 changed files with 834 additions and 821 deletions
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1
hw/super6502_fpga/sources.list
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@@ -1,3 +1,4 @@
src/sub/interfaces/sources.list
src/rtl/super_6502_fpga.sv
ip/sdram_controller/sdram_controller.v
src/sub/cpu_wrapper/sources.list

1
hw/super6502_fpga/src/sub/interfaces Submodule

Submodule hw/super6502_fpga/src/sub/interfaces added at 13c389dc18

24
hw/super6502_fpga/src/sub/network_processor/sim/cocotb/Makefile Normal file
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@@ -0,0 +1,24 @@
RTL_SRCS_LIST=$(REPO_TOP)/hw/super6502_fpga/sources.list
SIM_SRCS_LIST=tb/sources.list
RTL_SOURCES=$(shell rtl-manifest $(RTL_SRCS_LIST))
SIM_SOURCES=$(shell rtl-manifest $(SIM_SRCS_LIST))
VERILOG_SOURCES= $(INTF_SOURCES) $(RTL_SOURCES) $(SIM_SOURCES)
TOPLEVEL_LANG ?= verilog
SIM ?= verilator
EXTRA_ARGS += --trace --trace-fst --trace-structs -Wno-fatal -Wno-PINMISSING
TOPLEVEL = tb_top
GPI_IMPL := vpi
export PYTHONPATH := $(PWD)/tests:$(PYTHONPATH)
export TOPLEVEL_LANG
MODULE=sanity
include $(shell cocotb-config --makefiles)/Makefile.sim

1
hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tb/sources.list Normal file
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@@ -0,0 +1 @@
tb_top.sv

120
hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tb/tb_top.sv Normal file
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@@ -0,0 +1,120 @@
module tb_top(
input wire clk,
input wire rst,
output wire s_regs_axil_awready,
input wire s_regs_axil_awvalid,
input wire [31:0] s_regs_axil_awaddr,
input wire [2:0] s_regs_axil_awprot,
output wire s_regs_axil_wready,
input wire s_regs_axil_wvalid,
input wire [31:0] s_regs_axil_wdata,
input wire [3:0] s_regs_axil_wstrb,
input wire s_regs_axil_bready,
output wire s_regs_axil_bvalid,
output wire [1:0] s_regs_axil_bresp,
output wire s_regs_axil_arready,
input wire s_regs_axil_arvalid,
input wire [31:0] s_regs_axil_araddr,
input wire [2:0] s_regs_axil_arprot,
input wire s_regs_axil_rready,
output wire s_regs_axil_rvalid,
output wire [31:0] s_regs_axil_rdata,
output wire [1:0] s_regs_axil_rresp,
input wire m_dma_axil_awready,
output wire m_dma_axil_awvalid,
output wire [31:0] m_dma_axil_awaddr,
output wire [2:0] m_dma_axil_awprot,
input wire m_dma_axil_wready,
output wire m_dma_axil_wvalid,
output wire [31:0] m_dma_axil_wdata,
output wire [3:0] m_dma_axil_wstrb,
output wire m_dma_axil_bready,
input wire m_dma_axil_bvalid,
input wire [1:0] m_dma_axil_bresp,
input wire m_dma_axil_arready,
output wire m_dma_axil_arvalid,
output wire [31:0] m_dma_axil_araddr,
output wire [2:0] m_dma_axil_arprot,
output wire m_dma_axil_rready,
input wire m_dma_axil_rvalid,
input wire [31:0] m_dma_axil_rdata,
input wire [1:0] m_dma_axil_rresp,
//MII Interface
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er
);
axil_intf regs_axil();
axil_intf dma_axil();
assign dma_axil.awready = m_dma_axil_awready;
assign m_dma_axil_awvalid = dma_axil.awvalid;
assign m_dma_axil_awaddr = dma_axil.awaddr;
assign m_dma_axil_awprot = dma_axil.awprot;
assign dma_axil.wready = m_dma_axil_wready;
assign m_dma_axil_wvalid = dma_axil.wvalid;
assign m_dma_axil_wdata = dma_axil.wdata;
assign m_dma_axil_wstrb = dma_axil.wstrb;
assign m_dma_axil_bready = dma_axil.bready;
assign dma_axil.bvalid = m_dma_axil_bvalid;
assign dma_axil.bresp = m_dma_axil_bresp;
assign dma_axil.arready = m_dma_axil_arready;
assign m_dma_axil_arvalid = dma_axil.arvalid;
assign m_dma_axil_araddr = dma_axil.araddr;
assign m_dma_axil_arprot = dma_axil.arprot;
assign m_dma_axil_rready = dma_axil.rready;
assign dma_axil.rvalid = m_dma_axil_rvalid;
assign dma_axil.rdata = m_dma_axil_rdata;
assign dma_axil.rresp = m_dma_axil_rresp;
assign s_regs_axil_awready = regs_axil.awready;
assign regs_axil.awvalid = s_regs_axil_awvalid;
assign regs_axil.awaddr = s_regs_axil_awaddr;
assign regs_axil.awprot = s_regs_axil_awprot;
assign s_regs_axil_wready = regs_axil.wready;
assign regs_axil.wvalid = s_regs_axil_wvalid;
assign regs_axil.wdata = s_regs_axil_wdata;
assign regs_axil.wstrb = s_regs_axil_wstrb;
assign regs_axil.bready = s_regs_axil_bready;
assign s_regs_axil_bvalid = regs_axil.bvalid;
assign s_regs_axil_bresp = regs_axil.bresp;
assign s_regs_axil_arready = regs_axil.arready;
assign regs_axil.arvalid = s_regs_axil_arvalid;
assign regs_axil.araddr = s_regs_axil_araddr;
assign regs_axil.arprot = s_regs_axil_arprot;
assign regs_axil.rready = s_regs_axil_rready;
assign s_regs_axil_rvalid = regs_axil.rvalid;
assign s_regs_axil_rdata = regs_axil.rdata;
assign s_regs_axil_rresp = regs_axil.rresp;
network_processor #(
.NUM_TCP(8)
) u_network_processor (
.i_clk (clk),
.i_rst (rst),
.s_reg_axil (regs_axil),
.m_dma_axil (dma_axil),
.mii_rx_clk (mii_rx_clk),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_tx_clk (mii_tx_clk),
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er)
);
endmodule

44
hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/sanity.py Normal file
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@@ -0,0 +1,44 @@
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
from cocotb.triggers import RisingEdge
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam, AxiStreamBus, AxiStreamSink
import logging
from decimal import Decimal
CLK_PERIOD_NS = 10
class TB:
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, CLK_PERIOD_NS, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_regs_axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_dma_axil"), dut.clk, dut.rst, size=2**16)
async def cycle_reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk) # type: ignore
await RisingEdge(self.dut.clk) # type: ignore
self.dut.rst.value = 1
await RisingEdge(self.dut.clk) # type: ignore
await RisingEdge(self.dut.clk) # type: ignore
self.dut.rst.value = 0
await RisingEdge(self.dut.clk) # type: ignore
await RisingEdge(self.dut.clk) # type: ignore
@cocotb.test()
async def test_simple(dut):
tb = TB(dut)
await tb.cycle_reset()
await tb.axil_master.write_dword(0, 0xffff)
await Timer(Decimal(CLK_PERIOD_NS * 400), units='ns')

4
hw/super6502_fpga/src/sub/network_processor/sources.list
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@@ -10,4 +10,6 @@ src/network_processor.sv
src/tcp_state_manager.sv
src/tcp_stream.sv
src/tcp.sv
src/eth_wrapper.sv
src/eth_wrapper.sv
src/ip_arb_mux_wrapper.sv
src/ip_demux_wrapper.sv

55
hw/super6502_fpga/src/sub/network_processor/src/eth_wrapper.sv
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@@ -5,25 +5,8 @@ module eth_wrapper #(
input wire rst,
input wire clk_sys,
/*
* AXI input
*/
input wire [MAC_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [MAC_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [MAC_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [MAC_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
axis_intf.SLAVE tx_axis,
axis_intf.MASTER rx_axis,
/*
* MII interface
@@ -105,28 +88,28 @@ eth_mac_mii_fifo #(
.RX_FIFO_RAM_PIPELINE(1),
.RX_FRAME_FIFO(1)
) u_mac (
.rst (reset),
.logic_clk (clk_100),
.logic_rst (reset),
.rst (rst),
.logic_clk (clk_sys),
.logic_rst (rst),
.tx_axis_tdata (tx_axis_tdata),
.tx_axis_tkeep (tx_axis_tkeep),
.tx_axis_tvalid (tx_axis_tvalid),
.tx_axis_tready (tx_axis_tready),
.tx_axis_tlast (tx_axis_tlast),
.tx_axis_tdata (tx_axis.tdata),
.tx_axis_tkeep (tx_axis.tkeep),
.tx_axis_tvalid (tx_axis.tvalid),
.tx_axis_tready (tx_axis.tready),
.tx_axis_tlast (tx_axis.tlast),
.tx_axis_tuser ('0),
.rx_axis_tdata (rx_axis_tdata),
.rx_axis_tkeep (rx_axis_tkeep),
.rx_axis_tvalid (rx_axis_tvalid),
.rx_axis_tready (rx_axis_tready),
.rx_axis_tlast (rx_axis_tlast),
.rx_axis_tuser (rx_axis_tuser),
.rx_axis_tdata (rx_axis.tdata),
.rx_axis_tkeep (rx_axis.tkeep),
.rx_axis_tvalid (rx_axis.tvalid),
.rx_axis_tready (rx_axis.tready),
.rx_axis_tlast (rx_axis.tlast),
.rx_axis_tuser (rx_axis.tuser),
.mii_rx_clk (mii_rx_clk),
.mii_rxd (mii_rxd_mux),
.mii_rx_dv (mii_rx_dv_mux),
.mii_rx_er (mii_rx_er_mux),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_tx_clk (mii_tx_clk),
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),

154
hw/super6502_fpga/src/sub/network_processor/src/ip_arb_mux_wrapper.sv Normal file
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@@ -0,0 +1,154 @@
module ip_arb_mux_wrapper #(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
) (
input i_clk,
input i_rst,
ip_intf.SLAVE s_ip [S_COUNT],
ip_intf.MASTER m_ip
);
logic [S_COUNT-1:0] s_ip_hdr_valid;
logic [S_COUNT-1:0] s_ip_hdr_ready;
logic [S_COUNT*48-1:0] s_eth_dest_mac;
logic [S_COUNT*48-1:0] s_eth_src_mac;
logic [S_COUNT*16-1:0] s_eth_type;
logic [S_COUNT*4-1:0] s_ip_version;
logic [S_COUNT*4-1:0] s_ip_ihl;
logic [S_COUNT*6-1:0] s_ip_dscp;
logic [S_COUNT*2-1:0] s_ip_ecn;
logic [S_COUNT*16-1:0] s_ip_length;
logic [S_COUNT*16-1:0] s_ip_identification;
logic [S_COUNT*3-1:0] s_ip_flags;
logic [S_COUNT*13-1:0] s_ip_fragment_offset;
logic [S_COUNT*8-1:0] s_ip_ttl;
logic [S_COUNT*8-1:0] s_ip_protocol;
logic [S_COUNT*16-1:0] s_ip_header_checksum;
logic [S_COUNT*32-1:0] s_ip_source_ip;
logic [S_COUNT*32-1:0] s_ip_dest_ip;
logic [S_COUNT*DATA_WIDTH-1:0] s_ip_payload_axis_tdata;
logic [S_COUNT*KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep;
logic [S_COUNT-1:0] s_ip_payload_axis_tvalid;
logic [S_COUNT-1:0] s_ip_payload_axis_tready;
logic [S_COUNT-1:0] s_ip_payload_axis_tlast;
logic [S_COUNT*ID_WIDTH-1:0] s_ip_payload_axis_tid;
logic [S_COUNT*DEST_WIDTH-1:0] s_ip_payload_axis_tdest;
logic [S_COUNT*USER_WIDTH-1:0] s_ip_payload_axis_tuser;
generate
for (genvar i = 0; i < S_COUNT; i++) begin
assign s_ip_hdr_valid[i] = s_ip[i].ip_hdr_valid;
assign s_ip[i].ip_hdr_ready = s_ip_hdr_ready[i];
assign s_eth_dest_mac[i*48+:48] = s_ip[i].eth_dest_mac;
assign s_eth_src_mac[i*48+:48] = s_ip[i].eth_src_mac;
assign s_eth_type[i*16+:16] = s_ip[i].eth_type;
assign s_ip_version[i*4+:4] = s_ip[i].ip_version;
assign s_ip_ihl[i*4+:4] = s_ip[i].ip_ihl;
assign s_ip_dscp[i*6+:6] = s_ip[i].ip_dscp;
assign s_ip_ecn[i*2+:2] = s_ip[i].ip_ecn;
assign s_ip_length[i*16+:16] = s_ip[i].ip_length;
assign s_ip_identification[i*16+:16] = s_ip[i].ip_identification;
assign s_ip_flags[i*3+:3] = s_ip[i].ip_flags;
assign s_ip_fragment_offset[i*13+:13] = s_ip[i].ip_fragment_offset;
assign s_ip_ttl[i*8+:8] = s_ip[i].ip_ttl;
assign s_ip_protocol[i*8+:8] = s_ip[i].ip_protocol;
assign s_ip_header_checksum[i*16+:16] = s_ip[i].ip_header_checksum;
assign s_ip_source_ip[i*32+:32] = s_ip[i].ip_source_ip;
assign s_ip_dest_ip[i*32+:32] = s_ip[i].ip_dest_ip;
assign s_ip_payload_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH] = s_ip[i].ip_payload_axis_tdata;
assign s_ip_payload_axis_tkeep[i*KEEP_WIDTH+:KEEP_WIDTH] = s_ip[i].ip_payload_axis_tkeep;
assign s_ip_payload_axis_tvalid[i*KEEP_WIDTH+:KEEP_WIDTH] = s_ip[i].ip_payload_axis_tvalid;
assign s_ip[i].ip_payload_axis_tready = s_ip_payload_axis_tready[i];
assign s_ip_payload_axis_tlast[i] = s_ip[i].ip_payload_axis_tlast;
assign s_ip_payload_axis_tid[i*ID_WIDTH+:ID_WIDTH] = s_ip[i].ip_payload_axis_tid;
assign s_ip_payload_axis_tdest[i*DEST_WIDTH+:DEST_WIDTH] = s_ip[i].ip_payload_axis_tdest;
assign s_ip_payload_axis_tuser[i*USER_WIDTH+:USER_WIDTH] = s_ip[i].ip_payload_axis_tuser;
end
endgenerate
ip_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) u_arb_mux (
.clk (i_clk),
.rst (i_rst),
.s_ip_hdr_valid (s_ip_hdr_valid ),
.s_ip_hdr_ready (s_ip_hdr_ready ),
.s_eth_dest_mac (s_eth_dest_mac ),
.s_eth_src_mac (s_eth_src_mac ),
.s_eth_type (s_eth_type ),
.s_ip_version (s_ip_version ),
.s_ip_ihl (s_ip_ihl ),
.s_ip_dscp (s_ip_dscp ),
.s_ip_ecn (s_ip_ecn ),
.s_ip_length (s_ip_length ),
.s_ip_identification (s_ip_identification ),
.s_ip_flags (s_ip_flags ),
.s_ip_fragment_offset (s_ip_fragment_offset ),
.s_ip_ttl (s_ip_ttl ),
.s_ip_protocol (s_ip_protocol ),
.s_ip_header_checksum (s_ip_header_checksum ),
.s_ip_source_ip (s_ip_source_ip ),
.s_ip_dest_ip (s_ip_dest_ip ),
.s_ip_payload_axis_tdata (s_ip_payload_axis_tdata ),
.s_ip_payload_axis_tkeep (s_ip_payload_axis_tkeep ),
.s_ip_payload_axis_tvalid (s_ip_payload_axis_tvalid ),
.s_ip_payload_axis_tready (s_ip_payload_axis_tready ),
.s_ip_payload_axis_tlast (s_ip_payload_axis_tlast ),
.s_ip_payload_axis_tid (s_ip_payload_axis_tid ),
.s_ip_payload_axis_tdest (s_ip_payload_axis_tdest ),
.s_ip_payload_axis_tuser (s_ip_payload_axis_tuser ),
.m_ip_hdr_valid (m_ip.ip_hdr_valid ),
.m_ip_hdr_ready (m_ip.ip_hdr_ready ),
.m_eth_dest_mac (m_ip.eth_dest_mac ),
.m_eth_src_mac (m_ip.eth_src_mac ),
.m_eth_type (m_ip.eth_type ),
.m_ip_version (m_ip.ip_version ),
.m_ip_ihl (m_ip.ip_ihl ),
.m_ip_dscp (m_ip.ip_dscp ),
.m_ip_ecn (m_ip.ip_ecn ),
.m_ip_length (m_ip.ip_length ),
.m_ip_identification (m_ip.ip_identification ),
.m_ip_flags (m_ip.ip_flags ),
.m_ip_fragment_offset (m_ip.ip_fragment_offset ),
.m_ip_ttl (m_ip.ip_ttl ),
.m_ip_protocol (m_ip.ip_protocol ),
.m_ip_header_checksum (m_ip.ip_header_checksum ),
.m_ip_source_ip (m_ip.ip_source_ip ),
.m_ip_dest_ip (m_ip.ip_dest_ip ),
.m_ip_payload_axis_tdata (m_ip.ip_payload_axis_tdata ),
.m_ip_payload_axis_tkeep (m_ip.ip_payload_axis_tkeep ),
.m_ip_payload_axis_tvalid (m_ip.ip_payload_axis_tvalid ),
.m_ip_payload_axis_tready (m_ip.ip_payload_axis_tready ),
.m_ip_payload_axis_tlast (m_ip.ip_payload_axis_tlast ),
.m_ip_payload_axis_tid (m_ip.ip_payload_axis_tid ),
.m_ip_payload_axis_tdest (m_ip.ip_payload_axis_tdest ),
.m_ip_payload_axis_tuser (m_ip.ip_payload_axis_tuser )
);
endmodule

151
hw/super6502_fpga/src/sub/network_processor/src/ip_demux_wrapper.sv Normal file
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@@ -0,0 +1,151 @@
module ip_demux_wrapper #(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
ip_intf.SLAVE s_ip,
ip_intf.MASTER m_ip [M_COUNT],
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
logic [M_COUNT-1:0] m_ip_hdr_valid;
logic [M_COUNT-1:0] m_ip_hdr_ready;
logic [M_COUNT*48-1:0] m_eth_dest_mac;
logic [M_COUNT*48-1:0] m_eth_src_mac;
logic [M_COUNT*16-1:0] m_eth_type;
logic [M_COUNT*4-1:0] m_ip_version;
logic [M_COUNT*4-1:0] m_ip_ihl;
logic [M_COUNT*6-1:0] m_ip_dscp;
logic [M_COUNT*2-1:0] m_ip_ecn;
logic [M_COUNT*16-1:0] m_ip_length;
logic [M_COUNT*16-1:0] m_ip_identification;
logic [M_COUNT*3-1:0] m_ip_flags;
logic [M_COUNT*13-1:0] m_ip_fragment_offset;
logic [M_COUNT*8-1:0] m_ip_ttl;
logic [M_COUNT*8-1:0] m_ip_protocol;
logic [M_COUNT*16-1:0] m_ip_header_checksum;
logic [M_COUNT*32-1:0] m_ip_source_ip;
logic [M_COUNT*32-1:0] m_ip_dest_ip;
logic [M_COUNT*DATA_WIDTH-1:0] m_ip_payload_axis_tdata;
logic [M_COUNT*KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep;
logic [M_COUNT-1:0] m_ip_payload_axis_tvalid;
logic [M_COUNT-1:0] m_ip_payload_axis_tready;
logic [M_COUNT-1:0] m_ip_payload_axis_tlast;
logic [M_COUNT*ID_WIDTH-1:0] m_ip_payload_axis_tid;
logic [M_COUNT*DEST_WIDTH-1:0] m_ip_payload_axis_tdest;
logic [M_COUNT*USER_WIDTH-1:0] m_ip_payload_axis_tuser;
generate
for (genvar i = 0; i < M_COUNT; i++) begin
assign m_ip[i].ip_hdr_valid = m_ip_hdr_valid[i];
assign m_ip_hdr_ready[i] = m_ip[i].ip_hdr_ready;
assign m_ip[i].eth_dest_mac = m_eth_dest_mac[i*48+:48];
assign m_ip[i].eth_src_mac = m_eth_src_mac[i*48+:48];
assign m_ip[i].eth_type = m_eth_type[i*16+:16];
assign m_ip[i].ip_version = m_ip_version[i*4+:4];
assign m_ip[i].ip_ihl = m_ip_ihl[i*4+:4];
assign m_ip[i].ip_dscp = m_ip_dscp[i*6+:6];
assign m_ip[i].ip_ecn = m_ip_ecn[i*2+:2];
assign m_ip[i].ip_length = m_ip_length[i*16+:16];
assign m_ip[i].ip_identification = m_ip_identification[i*16+:16];
assign m_ip[i].ip_flags = m_ip_flags[i*3+:3];
assign m_ip[i].ip_fragment_offset = m_ip_fragment_offset[i*13+:13];
assign m_ip[i].ip_ttl = m_ip_ttl[i*8+:8];
assign m_ip[i].ip_protocol = m_ip_protocol[i*8+:8];
assign m_ip[i].ip_header_checksum = m_ip_header_checksum[i*16+:16];
assign m_ip[i].ip_source_ip = m_ip_source_ip[i*32+:32];
assign m_ip[i].ip_dest_ip = m_ip_dest_ip[i*32+:32];
assign m_ip[i].ip_payload_axis_tdata = m_ip_payload_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH];
assign m_ip[i].ip_payload_axis_tkeep = m_ip_payload_axis_tkeep[i*KEEP_WIDTH+:KEEP_WIDTH];
assign m_ip[i].ip_payload_axis_tvalid = m_ip_payload_axis_tvalid[i*KEEP_WIDTH+:KEEP_WIDTH];
assign m_ip_payload_axis_tready[i] = m_ip[i].ip_payload_axis_tready;
assign m_ip[i].ip_payload_axis_tlast = m_ip_payload_axis_tlast[i];
assign m_ip[i].ip_payload_axis_tid = m_ip_payload_axis_tid[i*ID_WIDTH+:ID_WIDTH];
assign m_ip[i].ip_payload_axis_tdest = m_ip_payload_axis_tdest[i*DEST_WIDTH+:DEST_WIDTH];
assign m_ip[i].ip_payload_axis_tuser = m_ip_payload_axis_tuser[i*USER_WIDTH+:USER_WIDTH];
end
endgenerate
ip_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) u_ip_demux (
.s_ip_hdr_valid (s_ip.ip_hdr_valid ),
.s_ip_hdr_ready (s_ip.ip_hdr_ready ),
.s_eth_dest_mac (s_ip.eth_dest_mac ),
.s_eth_src_mac (s_ip.eth_src_mac ),
.s_eth_type (s_ip.eth_type ),
.s_ip_version (s_ip.ip_version ),
.s_ip_ihl (s_ip.ip_ihl ),
.s_ip_dscp (s_ip.ip_dscp ),
.s_ip_ecn (s_ip.ip_ecn ),
.s_ip_length (s_ip.ip_length ),
.s_ip_identification (s_ip.ip_identification ),
.s_ip_flags (s_ip.ip_flags ),
.s_ip_fragment_offset (s_ip.ip_fragment_offset ),
.s_ip_ttl (s_ip.ip_ttl ),
.s_ip_protocol (s_ip.ip_protocol ),
.s_ip_header_checksum (s_ip.ip_header_checksum ),
.s_ip_source_ip (s_ip.ip_source_ip ),
.s_ip_dest_ip (s_ip.ip_dest_ip ),
.s_ip_payload_axis_tdata (s_ip.ip_payload_axis_tdata ),
.s_ip_payload_axis_tkeep (s_ip.ip_payload_axis_tkeep ),
.s_ip_payload_axis_tvalid (s_ip.ip_payload_axis_tvalid ),
.s_ip_payload_axis_tready (s_ip.ip_payload_axis_tready ),
.s_ip_payload_axis_tlast (s_ip.ip_payload_axis_tlast ),
.s_ip_payload_axis_tid (s_ip.ip_payload_axis_tid ),
.s_ip_payload_axis_tdest (s_ip.ip_payload_axis_tdest ),
.s_ip_payload_axis_tuser (s_ip.ip_payload_axis_tuser ),
.m_ip_hdr_valid (m_ip_hdr_valid ),
.m_ip_hdr_ready (m_ip_hdr_ready ),
.m_eth_dest_mac (m_eth_dest_mac ),
.m_eth_src_mac (m_eth_src_mac ),
.m_eth_type (m_eth_type ),
.m_ip_version (m_ip_version ),
.m_ip_ihl (m_ip_ihl ),
.m_ip_dscp (m_ip_dscp ),
.m_ip_ecn (m_ip_ecn ),
.m_ip_length (m_ip_length ),
.m_ip_identification (m_ip_identification ),
.m_ip_flags (m_ip_flags ),
.m_ip_fragment_offset (m_ip_fragment_offset ),
.m_ip_ttl (m_ip_ttl ),
.m_ip_protocol (m_ip_protocol ),
.m_ip_header_checksum (m_ip_header_checksum ),
.m_ip_source_ip (m_ip_source_ip ),
.m_ip_dest_ip (m_ip_dest_ip ),
.m_ip_payload_axis_tdata (m_ip_payload_axis_tdata ),
.m_ip_payload_axis_tkeep (m_ip_payload_axis_tkeep ),
.m_ip_payload_axis_tvalid (m_ip_payload_axis_tvalid ),
.m_ip_payload_axis_tready (m_ip_payload_axis_tready ),
.m_ip_payload_axis_tlast (m_ip_payload_axis_tlast ),
.m_ip_payload_axis_tid (m_ip_payload_axis_tid ),
.m_ip_payload_axis_tdest (m_ip_payload_axis_tdest ),
.m_ip_payload_axis_tuser (m_ip_payload_axis_tuser )
);
endmodule

595
hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv
View File

@@ -4,29 +4,8 @@ module network_processor #(
input i_clk,
input i_rst,
output logic s_reg_axil_awready,
input wire s_reg_axil_awvalid,
input wire [8:0] s_reg_axil_awaddr,
input wire [2:0] s_reg_axil_awprot,
output logic s_reg_axil_wready,
input wire s_reg_axil_wvalid,
input wire [31:0] s_reg_axil_wdata,
input wire [3:0] s_reg_axil_wstrb,
input wire s_reg_axil_bready,
output logic s_reg_axil_bvalid,
output logic [1:0] s_reg_axil_bresp,
output logic s_reg_axil_arready,
input wire s_reg_axil_arvalid,
input wire [8:0] s_reg_axil_araddr,
input wire [2:0] s_reg_axil_arprot,
input wire s_reg_axil_rready,
output logic s_reg_axil_rvalid,
output logic [31:0] s_reg_axil_rdata,
output logic [1:0] s_reg_axil_rresp,
// axil for m2s/s2m dma (can be combined into 1 or separate)
// axil for ring buffer managers
axil_intf.SLAVE s_reg_axil,
axil_intf.MASTER m_dma_axil,
//MII Interface
input wire mii_rx_clk,
@@ -52,184 +31,28 @@ module network_processor #(
`define PROTO_TCP 8'h6
`define PROTO_UDP 8'h11
localparam ICMP_IDX = 0;
localparam UDP_IDX = 1;
localparam TCP_IDX = 2;
localparam MAC_DATA_WIDTH = 8;
localparam AXIS_DATA_WIDTH = 8;
localparam AXIS_KEEP_WIDTH = ((AXIS_DATA_WIDTH+7)/8);
logic [AXIS_DATA_WIDTH-1:0] mac_tx_axis_tdata;
logic mac_tx_axis_tvalid;
logic mac_tx_axis_tready;
logic mac_tx_axis_tlast;
logic mac_tx_axis_tuser;
logic [AXIS_KEEP_WIDTH-1:0] mac_tx_axis_tkeep;
axis_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) mac_tx_axis();
axis_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) mac_rx_axis();
logic [AXIS_DATA_WIDTH-1:0] mac_rx_axis_tdata;
logic mac_rx_axis_tvalid;
logic mac_rx_axis_tready;
logic mac_rx_axis_tlast;
logic mac_rx_axis_tuser;
logic [AXIS_KEEP_WIDTH-1:0] mac_rx_axis_tkeep;
ip_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) mac_tx_ip();
ip_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) mac_rx_ip();
logic mac_tx_eth_hdr_valid;
logic mac_tx_eth_hdr_ready;
logic [47:0] mac_tx_eth_dest_mac;
logic [47:0] mac_tx_eth_src_mac;
logic [15:0] mac_tx_eth_type;
logic [AXIS_DATA_WIDTH-1:0] mac_tx_eth_payload_axis_tdata;
logic [AXIS_KEEP_WIDTH-1:0] mac_tx_eth_payload_axis_tkeep;
logic mac_tx_eth_payload_axis_tvalid;
logic mac_tx_eth_payload_axis_tready;
logic mac_tx_eth_payload_axis_tlast;
logic mac_tx_eth_payload_axis_tuser;
eth_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) mac_tx_eth();
eth_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) mac_rx_eth();
logic mac_rx_eth_hdr_valid;
logic mac_rx_eth_hdr_ready;
logic [47:0] mac_rx_eth_dest_mac;
logic [47:0] mac_rx_eth_src_mac;
logic [15:0] mac_rx_eth_type;
logic [AXIS_DATA_WIDTH-1:0] mac_rx_eth_payload_axis_tdata;
logic [AXIS_KEEP_WIDTH-1:0] mac_rx_eth_payload_axis_tkeep;
logic mac_rx_eth_payload_axis_tvalid;
logic mac_rx_eth_payload_axis_tready;
logic mac_rx_eth_payload_axis_tlast;
logic mac_rx_eth_payload_axis_tuser;
ip_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) ntw_tx_ip();
ip_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) ntw_rx_ip();
// tx is less because IP adds it automatically.
logic tx_ip_hdr_valid;
logic tx_ip_hdr_ready;
logic [5:0] tx_ip_dscp;
logic [1:0] tx_ip_ecn;
logic [15:0] tx_ip_length;
logic [7:0] tx_ip_ttl;
logic [7:0] tx_ip_protocol;
logic [31:0] tx_ip_source_ip;
logic [31:0] tx_ip_dest_ip;
logic [7:0] tx_ip_payload_axis_tdata;
logic tx_ip_payload_axis_tvalid;
logic tx_ip_payload_axis_tready;
logic tx_ip_payload_axis_tlast;
logic tx_ip_payload_axis_tuser;
logic tcp_rx_ip_hdr_valid;
logic tcp_rx_ip_hdr_ready;
logic [47:0] tcp_rx_ip_eth_dest_mac;
logic [47:0] tcp_rx_ip_eth_src_mac;
logic [15:0] tcp_rx_ip_eth_type;
logic [3:0] tcp_rx_ip_version;
logic [3:0] tcp_rx_ip_ihl;
logic [5:0] tcp_rx_ip_dscp;
logic [1:0] tcp_rx_ip_ecn;
logic [15:0] tcp_rx_ip_length;
logic [15:0] tcp_rx_ip_identification;
logic [2:0] tcp_rx_ip_flags;
logic [12:0] tcp_rx_ip_fragment_offset;
logic [7:0] tcp_rx_ip_ttl;
logic [7:0] tcp_rx_ip_protocol;
logic [15:0] tcp_rx_ip_header_checksum;
logic [31:0] tcp_rx_ip_source_ip;
logic [31:0] tcp_rx_ip_dest_ip;
logic [7:0] tcp_rx_ip_payload_axis_tdata;
logic tcp_rx_ip_payload_axis_tvalid;
logic tcp_rx_ip_payload_axis_tready;
logic tcp_rx_ip_payload_axis_tlast;
logic tcp_rx_ip_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic tcp_tx_ip_hdr_valid;
logic tcp_tx_ip_hdr_ready;
logic [5:0] tcp_tx_ip_dscp;
logic [1:0] tcp_tx_ip_ecn;
logic [15:0] tcp_tx_ip_length;
logic [7:0] tcp_tx_ip_ttl;
logic [7:0] tcp_tx_ip_protocol;
logic [31:0] tcp_tx_ip_source_ip;
logic [31:0] tcp_tx_ip_dest_ip;
logic [7:0] tcp_tx_ip_payload_axis_tdata;
logic tcp_tx_ip_payload_axis_tvalid;
logic tcp_tx_ip_payload_axis_tready;
logic tcp_tx_ip_payload_axis_tlast;
logic tcp_tx_ip_payload_axis_tuser;
logic udp_rx_ip_hdr_valid;
logic udp_rx_ip_hdr_ready;
logic [47:0] udp_rx_ip_eth_dest_mac;
logic [47:0] udp_rx_ip_eth_src_mac;
logic [15:0] udp_rx_ip_eth_type;
logic [3:0] udp_rx_ip_version;
logic [3:0] udp_rx_ip_ihl;
logic [5:0] udp_rx_ip_dscp;
logic [1:0] udp_rx_ip_ecn;
logic [15:0] udp_rx_ip_length;
logic [15:0] udp_rx_ip_identification;
logic [2:0] udp_rx_ip_flags;
logic [12:0] udp_rx_ip_fragment_offset;
logic [7:0] udp_rx_ip_ttl;
logic [7:0] udp_rx_ip_protocol;
logic [15:0] udp_rx_ip_header_checksum;
logic [31:0] udp_rx_ip_source_ip;
logic [31:0] udp_rx_ip_dest_ip;
logic [7:0] udp_rx_ip_payload_axis_tdata;
logic udp_rx_ip_payload_axis_tvalid;
logic udp_rx_ip_payload_axis_tready;
logic udp_rx_ip_payload_axis_tlast;
logic udp_rx_ip_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic udp_tx_ip_hdr_valid;
logic udp_tx_ip_hdr_ready;
logic [5:0] udp_tx_ip_dscp;
logic [1:0] udp_tx_ip_ecn;
logic [15:0] udp_tx_ip_length;
logic [7:0] udp_tx_ip_ttl;
logic [7:0] udp_tx_ip_protocol;
logic [31:0] udp_tx_ip_source_ip;
logic [31:0] udp_tx_ip_dest_ip;
logic [7:0] udp_tx_ip_payload_axis_tdata;
logic udp_tx_ip_payload_axis_tvalid;
logic udp_tx_ip_payload_axis_tready;
logic udp_tx_ip_payload_axis_tlast;
logic udp_tx_ip_payload_axis_tuser;
logic icmp_rx_ip_hdr_valid;
logic icmp_rx_ip_hdr_ready;
logic [47:0] icmp_rx_ip_eth_dest_mac;
logic [47:0] icmp_rx_ip_eth_src_mac;
logic [15:0] icmp_rx_ip_eth_type;
logic [3:0] icmp_rx_ip_version;
logic [3:0] icmp_rx_ip_ihl;
logic [5:0] icmp_rx_ip_dscp;
logic [1:0] icmp_rx_ip_ecn;
logic [15:0] icmp_rx_ip_length;
logic [15:0] icmp_rx_ip_identification;
logic [2:0] icmp_rx_ip_flags;
logic [12:0] icmp_rx_ip_fragment_offset;
logic [7:0] icmp_rx_ip_ttl;
logic [7:0] icmp_rx_ip_protocol;
logic [15:0] icmp_rx_ip_header_checksum;
logic [31:0] icmp_rx_ip_source_ip;
logic [31:0] icmp_rx_ip_dest_ip;
logic [7:0] icmp_rx_ip_payload_axis_tdata;
logic icmp_rx_ip_payload_axis_tvalid;
logic icmp_rx_ip_payload_axis_tready;
logic icmp_rx_ip_payload_axis_tlast;
logic icmp_rx_ip_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic icmp_tx_ip_hdr_valid;
logic icmp_tx_ip_hdr_ready;
logic [5:0] icmp_tx_ip_dscp;
logic [1:0] icmp_tx_ip_ecn;
logic [15:0] icmp_tx_ip_length;
logic [7:0] icmp_tx_ip_ttl;
logic [7:0] icmp_tx_ip_protocol;
logic [31:0] icmp_tx_ip_source_ip;
logic [31:0] icmp_tx_ip_dest_ip;
logic [7:0] icmp_tx_ip_payload_axis_tdata;
logic icmp_tx_ip_payload_axis_tvalid;
logic icmp_tx_ip_payload_axis_tready;
logic icmp_tx_ip_payload_axis_tlast;
logic icmp_tx_ip_payload_axis_tuser;
ip_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) proto_rx_ip[3]();
ip_intf #(.DATA_WIDTH(MAC_DATA_WIDTH)) proto_tx_ip[3]();
ntw_top_regfile_pkg::ntw_top_regfile__in_t hwif_in;
ntw_top_regfile_pkg::ntw_top_regfile__out_t hwif_out;
@@ -238,25 +61,25 @@ ntw_top_regfile u_ntw_top_regfile (
.clk (i_clk),
.rst (i_rst),
.s_axil_awready (s_reg_axil_awready),
.s_axil_awvalid (s_reg_axil_awvalid),
.s_axil_awaddr (s_reg_axil_awaddr),
.s_axil_awprot (s_reg_axil_awprot),
.s_axil_wready (s_reg_axil_wready),
.s_axil_wvalid (s_reg_axil_wvalid),
.s_axil_wdata (s_reg_axil_wdata),
.s_axil_wstrb (s_reg_axil_wstrb),
.s_axil_bready (s_reg_axil_bready),
.s_axil_bvalid (s_reg_axil_bvalid),
.s_axil_bresp (s_reg_axil_bresp),
.s_axil_arready (s_reg_axil_arready),
.s_axil_arvalid (s_reg_axil_arvalid),
.s_axil_araddr (s_reg_axil_araddr),
.s_axil_arprot (s_reg_axil_arprot),
.s_axil_rready (s_reg_axil_rready),
.s_axil_rvalid (s_reg_axil_rvalid),
.s_axil_rdata (s_reg_axil_rdata),
.s_axil_rresp (s_reg_axil_rresp),
.s_axil_awready (s_reg_axil.awready),
.s_axil_awvalid (s_reg_axil.awvalid),
.s_axil_awaddr (s_reg_axil.awaddr),
.s_axil_awprot (s_reg_axil.awprot),
.s_axil_wready (s_reg_axil.wready),
.s_axil_wvalid (s_reg_axil.wvalid),
.s_axil_wdata (s_reg_axil.wdata),
.s_axil_wstrb (s_reg_axil.wstrb),
.s_axil_bready (s_reg_axil.bready),
.s_axil_bvalid (s_reg_axil.bvalid),
.s_axil_bresp (s_reg_axil.bresp),
.s_axil_arready (s_reg_axil.arready),
.s_axil_arvalid (s_reg_axil.arvalid),
.s_axil_araddr (s_reg_axil.araddr),
.s_axil_arprot (s_reg_axil.arprot),
.s_axil_rready (s_reg_axil.rready),
.s_axil_rvalid (s_reg_axil.rvalid),
.s_axil_rdata (s_reg_axil.rdata),
.s_axil_rresp (s_reg_axil.rresp),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
@@ -269,6 +92,19 @@ eth_wrapper #(
.rst (i_rst),
.clk_sys (i_clk),
.s_cpuif_req (hwif_out.mac.req),
.s_cpuif_req_is_wr (hwif_out.mac.req_is_wr),
.s_cpuif_addr (hwif_out.mac.addr),
.s_cpuif_wr_data (hwif_out.mac.wr_data),
.s_cpuif_wr_biten (hwif_out.mac.wr_biten),
.s_cpuif_req_stall_wr (),
.s_cpuif_req_stall_rd (),
.s_cpuif_rd_ack (hwif_in.mac.rd_ack),
.s_cpuif_rd_err (),
.s_cpuif_rd_data (hwif_in.mac.rd_data),
.s_cpuif_wr_ack (hwif_in.mac.wr_ack),
.s_cpuif_wr_err (),
// MII
.mii_rx_clk (mii_rx_clk),
.mii_rxd (mii_rxd),
@@ -279,19 +115,8 @@ eth_wrapper #(
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.tx_axis_tdata (mac_tx_axis_tdata),
.tx_axis_tvalid (mac_tx_axis_tvalid),
.tx_axis_tready (mac_tx_axis_tready),
.tx_axis_tlast (mac_tx_axis_tlast),
.tx_axis_tuser (mac_tx_axis_tuser),
.tx_axis_tkeep (mac_tx_axis_tkeep),
.rx_axis_tdata (mac_rx_axis_tdata),
.rx_axis_tvalid (mac_rx_axis_tvalid),
.rx_axis_tready (mac_rx_axis_tready),
.rx_axis_tlast (mac_rx_axis_tlast),
.rx_axis_tuser (mac_rx_axis_tuser),
.rx_axis_tkeep (mac_rx_axis_tkeep),
.tx_axis (mac_tx_axis),
.rx_axis (mac_rx_axis),
.Mdi (i_Mdi),
.Mdo (o_Mdo),
@@ -305,24 +130,24 @@ eth_axis_rx #(
.clk (i_clk),
.rst (i_rst),
.s_axis_tdata (mac_rx_axis_tdata),
.s_axis_tvalid (mac_rx_axis_tvalid),
.s_axis_tready (mac_rx_axis_tready),
.s_axis_tlast (mac_rx_axis_tlast),
.s_axis_tuser (mac_rx_axis_tuser),
.s_axis_tkeep (mac_rx_axis_tkeep),
.s_axis_tdata (mac_rx_axis.tdata),
.s_axis_tvalid (mac_rx_axis.tvalid),
.s_axis_tready (mac_rx_axis.tready),
.s_axis_tlast (mac_rx_axis.tlast),
.s_axis_tuser (mac_rx_axis.tuser),
.s_axis_tkeep (mac_rx_axis.tkeep),
.m_eth_hdr_valid (mac_rx_eth_hdr_valid),
.m_eth_hdr_ready (mac_rx_eth_hdr_ready),
.m_eth_dest_mac (mac_rx_eth_dest_mac),
.m_eth_src_mac (mac_rx_eth_src_mac),
.m_eth_type (mac_rx_eth_type),
.m_eth_payload_axis_tdata (mac_rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep (mac_rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid (mac_rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready (mac_rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast (mac_rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser (mac_rx_eth_payload_axis_tuser),
.m_eth_hdr_valid (mac_rx_eth.eth_hdr_valid),
.m_eth_hdr_ready (mac_rx_eth.eth_hdr_ready),
.m_eth_dest_mac (mac_rx_eth.eth_dest_mac),
.m_eth_src_mac (mac_rx_eth.eth_src_mac),
.m_eth_type (mac_rx_eth.eth_type),
.m_eth_payload_axis_tdata (mac_rx_eth.eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep (mac_rx_eth.eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid (mac_rx_eth.eth_payload_axis_tvalid),
.m_eth_payload_axis_tready (mac_rx_eth.eth_payload_axis_tready),
.m_eth_payload_axis_tlast (mac_rx_eth.eth_payload_axis_tlast),
.m_eth_payload_axis_tuser (mac_rx_eth.eth_payload_axis_tuser),
.busy (),
.error_header_early_termination () // We can add this to a register
@@ -334,24 +159,24 @@ eth_axis_tx #(
.clk (i_clk),
.rst (i_rst),
.s_eth_hdr_valid (mac_tx_eth_hdr_valid),
.s_eth_hdr_ready (mac_tx_eth_hdr_ready),
.s_eth_dest_mac (mac_tx_eth_dest_mac),
.s_eth_src_mac (mac_tx_eth_src_mac),
.s_eth_type (mac_tx_eth_type),
.s_eth_payload_axis_tdata (mac_tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep (mac_tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid (mac_tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready (mac_tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast (mac_tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser (mac_tx_eth_payload_axis_tuser),
.s_eth_hdr_valid (mac_tx_eth.eth_hdr_valid),
.s_eth_hdr_ready (mac_tx_eth.eth_hdr_ready),
.s_eth_dest_mac (mac_tx_eth.eth_dest_mac),
.s_eth_src_mac (mac_tx_eth.eth_src_mac),
.s_eth_type (mac_tx_eth.eth_type),
.s_eth_payload_axis_tdata (mac_tx_eth.eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep (mac_tx_eth.eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid (mac_tx_eth.eth_payload_axis_tvalid),
.s_eth_payload_axis_tready (mac_tx_eth.eth_payload_axis_tready),
.s_eth_payload_axis_tlast (mac_tx_eth.eth_payload_axis_tlast),
.s_eth_payload_axis_tuser (mac_tx_eth.eth_payload_axis_tuser),
.m_axis_tdata (mac_tx_axis_tdata),
.m_axis_tvalid (mac_tx_axis_tvalid),
.m_axis_tready (mac_tx_axis_tready),
.m_axis_tlast (mac_tx_axis_tlast),
.m_axis_tuser (mac_tx_axis_tuser),
.m_axis_tkeep (mac_tx_axis_tkeep),
.m_axis_tdata (mac_tx_axis.tdata),
.m_axis_tvalid (mac_tx_axis.tvalid),
.m_axis_tready (mac_tx_axis.tready),
.m_axis_tlast (mac_tx_axis.tlast),
.m_axis_tuser (mac_tx_axis.tuser),
.m_axis_tkeep (mac_tx_axis.tkeep),
.busy ()
);
@@ -368,66 +193,66 @@ ip_complete #(
.clk (i_clk),
.rst (i_rst),
.s_eth_hdr_valid (mac_rx_eth_hdr_valid),
.s_eth_hdr_ready (mac_rx_eth_hdr_ready),
.s_eth_dest_mac (mac_rx_eth_dest_mac),
.s_eth_src_mac (mac_rx_eth_src_mac),
.s_eth_type (mac_rx_eth_type),
.s_eth_payload_axis_tdata (mac_rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid (mac_rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready (mac_rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast (mac_rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser (mac_rx_eth_payload_axis_tuser),
.s_eth_hdr_valid (mac_rx_eth.eth_hdr_valid),
.s_eth_hdr_ready (mac_rx_eth.eth_hdr_ready),
.s_eth_dest_mac (mac_rx_eth.eth_dest_mac),
.s_eth_src_mac (mac_rx_eth.eth_src_mac),
.s_eth_type (mac_rx_eth.eth_type),
.s_eth_payload_axis_tdata (mac_rx_eth.eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid (mac_rx_eth.eth_payload_axis_tvalid),
.s_eth_payload_axis_tready (mac_rx_eth.eth_payload_axis_tready),
.s_eth_payload_axis_tlast (mac_rx_eth.eth_payload_axis_tlast),
.s_eth_payload_axis_tuser (mac_rx_eth.eth_payload_axis_tuser),
.m_eth_hdr_valid (mac_tx_eth_hdr_valid),
.m_eth_hdr_ready (mac_tx_eth_hdr_ready),
.m_eth_dest_mac (mac_tx_eth_dest_mac),
.m_eth_src_mac (mac_tx_eth_src_mac),
.m_eth_type (mac_tx_eth_type),
.m_eth_payload_axis_tdata (mac_tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid (mac_tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready (mac_tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast (mac_tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser (mac_tx_eth_payload_axis_tuser),
.m_eth_hdr_valid (mac_tx_eth.eth_hdr_valid),
.m_eth_hdr_ready (mac_tx_eth.eth_hdr_ready),
.m_eth_dest_mac (mac_tx_eth.eth_dest_mac),
.m_eth_src_mac (mac_tx_eth.eth_src_mac),
.m_eth_type (mac_tx_eth.eth_type),
.m_eth_payload_axis_tdata (mac_tx_eth.eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid (mac_tx_eth.eth_payload_axis_tvalid),
.m_eth_payload_axis_tready (mac_tx_eth.eth_payload_axis_tready),
.m_eth_payload_axis_tlast (mac_tx_eth.eth_payload_axis_tlast),
.m_eth_payload_axis_tuser (mac_tx_eth.eth_payload_axis_tuser),
.s_ip_hdr_valid (tx_ip_hdr_valid),
.s_ip_hdr_ready (tx_ip_hdr_ready),
.s_ip_dscp (tx_ip_dscp),
.s_ip_ecn (tx_ip_ecn),
.s_ip_length (tx_ip_length),
.s_ip_ttl (tx_ip_ttl),
.s_ip_protocol (tx_ip_protocol),
.s_ip_source_ip (tx_ip_source_ip),
.s_ip_dest_ip (tx_ip_dest_ip),
.s_ip_payload_axis_tdata (tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid (tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready (tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast (tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser (tx_ip_payload_axis_tuser),
.s_ip_hdr_valid (ntw_tx_ip.ip_hdr_valid),
.s_ip_hdr_ready (ntw_tx_ip.ip_hdr_ready),
.s_ip_dscp (ntw_tx_ip.ip_dscp),
.s_ip_ecn (ntw_tx_ip.ip_ecn),
.s_ip_length (ntw_tx_ip.ip_length),
.s_ip_ttl (ntw_tx_ip.ip_ttl),
.s_ip_protocol (ntw_tx_ip.ip_protocol),
.s_ip_source_ip (ntw_tx_ip.ip_source_ip),
.s_ip_dest_ip (ntw_tx_ip.ip_dest_ip),
.s_ip_payload_axis_tdata (ntw_tx_ip.ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid (ntw_tx_ip.ip_payload_axis_tvalid),
.s_ip_payload_axis_tready (ntw_tx_ip.ip_payload_axis_tready),
.s_ip_payload_axis_tlast (ntw_tx_ip.ip_payload_axis_tlast),
.s_ip_payload_axis_tuser (ntw_tx_ip.ip_payload_axis_tuser),
.m_ip_hdr_valid (rx_ip_hdr_valid),
.m_ip_hdr_ready (rx_ip_hdr_ready),
.m_ip_eth_dest_mac (rx_ip_eth_dest_mac),
.m_ip_eth_src_mac (rx_ip_eth_src_mac),
.m_ip_eth_type (rx_ip_eth_type),
.m_ip_version (rx_ip_version),
.m_ip_ihl (rx_ip_ihl),
.m_ip_dscp (rx_ip_dscp),
.m_ip_ecn (rx_ip_ecn),
.m_ip_length (rx_ip_length),
.m_ip_identification (rx_ip_identification),
.m_ip_flags (rx_ip_flags),
.m_ip_fragment_offset (rx_ip_fragment_offset),
.m_ip_ttl (rx_ip_ttl),
.m_ip_protocol (rx_ip_protocol),
.m_ip_header_checksum (rx_ip_header_checksum),
.m_ip_source_ip (rx_ip_source_ip),
.m_ip_dest_ip (rx_ip_dest_ip),
.m_ip_payload_axis_tdata (rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid (rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready (rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast (rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser (rx_ip_payload_axis_tuser),
.m_ip_hdr_valid (ntw_rx_ip.ip_hdr_valid),
.m_ip_hdr_ready (ntw_rx_ip.ip_hdr_ready),
.m_ip_eth_dest_mac (ntw_rx_ip.eth_dest_mac),
.m_ip_eth_src_mac (ntw_rx_ip.eth_src_mac),
.m_ip_eth_type (ntw_rx_ip.eth_type),
.m_ip_version (ntw_rx_ip.ip_version),
.m_ip_ihl (ntw_rx_ip.ip_ihl),
.m_ip_dscp (ntw_rx_ip.ip_dscp),
.m_ip_ecn (ntw_rx_ip.ip_ecn),
.m_ip_length (ntw_rx_ip.ip_length),
.m_ip_identification (ntw_rx_ip.ip_identification),
.m_ip_flags (ntw_rx_ip.ip_flags),
.m_ip_fragment_offset (ntw_rx_ip.ip_fragment_offset),
.m_ip_ttl (ntw_rx_ip.ip_ttl),
.m_ip_protocol (ntw_rx_ip.ip_protocol),
.m_ip_header_checksum (ntw_rx_ip.ip_header_checksum),
.m_ip_source_ip (ntw_rx_ip.ip_source_ip),
.m_ip_dest_ip (ntw_rx_ip.ip_dest_ip),
.m_ip_payload_axis_tdata (ntw_rx_ip.ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid (ntw_rx_ip.ip_payload_axis_tvalid),
.m_ip_payload_axis_tready (ntw_rx_ip.ip_payload_axis_tready),
.m_ip_payload_axis_tlast (ntw_rx_ip.ip_payload_axis_tlast),
.m_ip_payload_axis_tuser (ntw_rx_ip.ip_payload_axis_tuser),
.rx_busy (), // should go to stats register
.tx_busy (), // should go to stats register
@@ -447,139 +272,45 @@ ip_complete #(
logic ip_demux_drop;
assign ip_demux_drop = !((rx_ip_protocol == `PROTO_ICMP) || (rx_ip_protocol == `PROTO_UDP) || (rx_ip_protocol == `PROTO_TCP));
assign ip_demux_drop = !((ntw_rx_ip.ip_protocol == `PROTO_ICMP) || (ntw_rx_ip.ip_protocol == `PROTO_UDP) || (ntw_rx_ip.ip_protocol == `PROTO_TCP));
logic [1:0] ip_demux_sel;
assign ip_demux_sel = (rx_ip_protocol == `PROTO_ICMP) ? 2'h2 : (rx_ip_protocol == `PROTO_UDP) ? 2'h1 : 2'h0;
assign ip_demux_sel = (ntw_rx_ip.ip_protocol == `PROTO_ICMP) ? 2'h2 : (ntw_rx_ip.ip_protocol == `PROTO_UDP) ? 2'h1 : 2'h0;
ip_demux #(
ip_demux_wrapper #(
.M_COUNT(3),
.DATA_WIDTH(MAC_DATA_WIDTH)
) u_ip_demux (
.clk (i_clk),
.rst (i_rst),
.s_ip_hdr_valid (rx_ip_hdr_valid),
.s_ip_hdr_ready (rx_ip_hdr_ready),
.s_eth_dest_mac (rx_ip_eth_dest_mac),
.s_eth_src_mac (rx_ip_eth_src_mac),
.s_eth_type (rx_ip_eth_type),
.s_ip_version (rx_ip_version),
.s_ip_ihl (rx_ip_ihl),
.s_ip_dscp (rx_ip_dscp),
.s_ip_ecn (rx_ip_ecn),
.s_ip_length (rx_ip_length),
.s_ip_identification (rx_ip_identification),
.s_ip_flags (rx_ip_flags),
.s_ip_fragment_offset (rx_ip_fragment_offset),
.s_ip_ttl (rx_ip_ttl),
.s_ip_protocol (rx_ip_protocol),
.s_ip_header_checksum (rx_ip_header_checksum),
.s_ip_source_ip (rx_ip_source_ip),
.s_ip_dest_ip (rx_ip_dest_ip),
.s_ip_payload_axis_tdata (rx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid (rx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready (rx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast (rx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser (rx_ip_payload_axis_tuser),
.m_ip_hdr_valid ({icmp_rx_ip_hdr_valid, udp_rx_ip_hdr_valid, tcp_rx_ip_hdr_valid}),
.m_ip_hdr_ready ({icmp_rx_ip_hdr_ready, udp_rx_ip_hdr_ready, tcp_rx_ip_hdr_ready}),
.m_eth_dest_mac ({icmp_rx_ip_eth_dest_mac, udp_rx_ip_eth_dest_mac, tcp_rx_ip_eth_dest_mac}),
.m_eth_src_mac ({icmp_rx_ip_eth_src_mac, udp_rx_ip_eth_src_mac, tcp_rx_ip_eth_src_mac}),
.m_eth_type ({icmp_rx_ip_eth_type, udp_rx_ip_eth_type, tcp_rx_ip_eth_type}),
.m_ip_version ({icmp_rx_ip_version, udp_rx_ip_version, tcp_rx_ip_version}),
.m_ip_ihl ({icmp_rx_ip_ihl, udp_rx_ip_ihl, tcp_rx_ip_ihl}),
.m_ip_dscp ({icmp_rx_ip_dscp, udp_rx_ip_dscp, tcp_rx_ip_dscp}),
.m_ip_ecn ({icmp_rx_ip_ecn, udp_rx_ip_ecn, tcp_rx_ip_ecn}),
.m_ip_length ({icmp_rx_ip_length, udp_rx_ip_length, tcp_rx_ip_length}),
.m_ip_identification ({icmp_rx_ip_identification, udp_rx_ip_identification, tcp_rx_ip_identification}),
.m_ip_flags ({icmp_rx_ip_flags, udp_rx_ip_flags, tcp_rx_ip_flags}),
.m_ip_fragment_offset ({icmp_rx_ip_fragment_offset, udp_rx_ip_fragment_offset, tcp_rx_ip_fragment_offset}),
.m_ip_ttl ({icmp_rx_ip_ttl, udp_rx_ip_ttl, tcp_rx_ip_ttl}),
.m_ip_protocol ({icmp_rx_ip_protocol, udp_rx_ip_protocol, tcp_rx_ip_protocol}),
.m_ip_header_checksum ({icmp_rx_ip_header_checksum, udp_rx_ip_header_checksum, tcp_rx_ip_header_checksum}),
.m_ip_source_ip ({icmp_rx_ip_source_ip, udp_rx_ip_source_ip, tcp_rx_ip_source_ip}),
.m_ip_dest_ip ({icmp_rx_ip_dest_ip, udp_rx_ip_dest_ip, tcp_rx_ip_dest_ip}),
.m_ip_payload_axis_tdata ({icmp_rx_ip_payload_axis_tdata, udp_rx_ip_payload_axis_tdata, tcp_rx_ip_payload_axis_tdata}),
.m_ip_payload_axis_tkeep (),
.m_ip_payload_axis_tvalid ({icmp_rx_ip_payload_axis_tvalid, udp_rx_ip_payload_axis_tvalid, tcp_rx_ip_payload_axis_tvalid}),
.m_ip_payload_axis_tready ({icmp_rx_ip_payload_axis_tready, udp_rx_ip_payload_axis_tready, tcp_rx_ip_payload_axis_tready}),
.m_ip_payload_axis_tlast ({icmp_rx_ip_payload_axis_tlast, udp_rx_ip_payload_axis_tlast, tcp_rx_ip_payload_axis_tlast}),
.m_ip_payload_axis_tid (),
.m_ip_payload_axis_tdest (),
.m_ip_payload_axis_tuser ({icmp_rx_ip_payload_axis_tuser, udp_rx_ip_payload_axis_tuser, tcp_rx_ip_payload_axis_tuser}),
.s_ip (ntw_rx_ip),
.m_ip (proto_rx_ip),
.enable ('1),
.drop (ip_demux_drop),
.select (ip_demux_sel)
);
assign icmp_rx_ip_hdr_ready = '1;
assign icmp_rx_ip_payload_axis_tready = '1;
assign udp_rx_ip_hdr_ready = '1;
assign udp_rx_ip_payload_axis_tready = '1;
assign proto_rx_ip[ICMP_IDX].ip_hdr_ready = '1;
assign proto_rx_ip[ICMP_IDX].ip_payload_axis_tready = '1;
assign proto_rx_ip[UDP_IDX].ip_hdr_ready = '1;
assign proto_rx_ip[UDP_IDX].ip_payload_axis_tready = '1;
ip_arb_mux #(
ip_arb_mux_wrapper #(
.S_COUNT(3),
.DATA_WIDTH(MAC_DATA_WIDTH)
) u_ip_arb_mux (
.clk (i_clk),
.rst (i_rst),
) u_ip_arb_mux (
.i_clk (i_clk),
.i_rst (i_rst),
.s_ip_hdr_valid ({icmp_tx_ip_hdr_valid, udp_tx_ip_hdr_valid, tcp_tx_ip_hdr_valid}),
.s_ip_hdr_ready ({icmp_tx_ip_hdr_ready, udp_tx_ip_hdr_ready, tcp_tx_ip_hdr_ready}),
.s_eth_dest_mac ('0),
.s_eth_src_mac ('0),
.s_eth_type ('0),
.s_ip_version ('0),
.s_ip_ihl ('0),
.s_ip_dscp ({icmp_tx_ip_dscp, udp_tx_ip_dscp, tcp_tx_ip_dscp}),
.s_ip_ecn ({icmp_tx_ip_ecn, udp_tx_ip_ecn, tcp_tx_ip_ecn}),
.s_ip_length ({icmp_tx_ip_length, udp_tx_ip_length, tcp_tx_ip_length}),
.s_ip_identification ('0),
.s_ip_flags ('0),
.s_ip_fragment_offset ('0),
.s_ip_ttl ({icmp_tx_ip_ttl, udp_tx_ip_ttl, tcp_tx_ip_ttl}),
.s_ip_protocol ({icmp_tx_ip_protocol, udp_tx_ip_protocol, tcp_tx_ip_protocol}),
.s_ip_header_checksum ('0),
.s_ip_source_ip ({icmp_tx_ip_source_ip, udp_tx_ip_source_ip, tcp_tx_ip_source_ip}),
.s_ip_dest_ip ({icmp_tx_ip_dest_ip, udp_tx_ip_dest_ip, tcp_tx_ip_dest_ip}),
.s_ip_payload_axis_tdata ({icmp_tx_ip_payload_axis_tdata, udp_tx_ip_payload_axis_tdata, tcp_tx_ip_payload_axis_tdata}),
.s_ip_payload_axis_tkeep ('1),
.s_ip_payload_axis_tvalid ({icmp_tx_ip_payload_axis_tvalid, udp_tx_ip_payload_axis_tvalid, tcp_tx_ip_payload_axis_tvalid}),
.s_ip_payload_axis_tready ({icmp_tx_ip_payload_axis_tready, udp_tx_ip_payload_axis_tready, tcp_tx_ip_payload_axis_tready}),
.s_ip_payload_axis_tlast ({icmp_tx_ip_payload_axis_tlast, udp_tx_ip_payload_axis_tlast, tcp_tx_ip_payload_axis_tlast}),
.s_ip_payload_axis_tid ('0),
.s_ip_payload_axis_tdest ('0),
.s_ip_payload_axis_tuser ({icmp_tx_ip_payload_axis_tuser, udp_tx_ip_payload_axis_tuser, tcp_tx_ip_payload_axis_tuser}),
.m_ip_hdr_valid (tx_ip_hdr_valid),
.m_ip_hdr_ready (tx_ip_hdr_ready),
.m_eth_dest_mac (),
.m_eth_src_mac (),
.m_eth_type (),
.m_ip_version (),
.m_ip_ihl (),
.m_ip_dscp (tx_ip_dscp),
.m_ip_ecn (tx_ip_ecn),
.m_ip_length (),
.m_ip_identification (),
.m_ip_flags (),
.m_ip_fragment_offset (),
.m_ip_ttl (tx_ip_ttl),
.m_ip_protocol (tx_ip_protocol),
.m_ip_header_checksum (),
.m_ip_source_ip (tx_ip_source_ip),
.m_ip_dest_ip (tx_ip_dest_ip),
.m_ip_payload_axis_tdata (tx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid (tx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready (tx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast (tx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser (tx_ip_payload_axis_tuser)
.s_ip (proto_tx_ip),
.m_ip (ntw_tx_ip)
);
axil_intf dummy();
tcp #(
.NUM_TCP(NUM_TCP)
) tcp (
@@ -597,6 +328,12 @@ tcp #(
.s_cpuif_rd_err (),
.s_cpuif_rd_data (hwif_in.tcp_top.rd_data),
.s_cpuif_wr_ack (hwif_in.tcp_top.wr_ack),
.s_cpuif_wr_err ()
.s_cpuif_wr_err (),
.s_ip (proto_rx_ip[TCP_IDX]),
.m_ip (proto_tx_ip[TCP_IDX]),
.m_dma_m2s_axi (m_dma_axil), // HACK
.m_dma_s2m_axi (dummy)
);
endmodule

4
hw/super6502_fpga/src/sub/network_processor/src/regs/ntw_top_regs.rdl
View File

@@ -1,4 +1,4 @@
addrmap ntw_top_regfile {
external mac_regs mac;
external tcp_top_regfile tcp_top;
external mac_regs mac @ 0x0;
external tcp_top_regfile tcp_top @ 0x200;
};

425
hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
View File

@@ -21,93 +21,19 @@ module tcp #(
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_ip_eth_dest_mac,
input wire [47:0] s_ip_eth_src_mac,
input wire [15:0] s_ip_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
ip_intf.SLAVE s_ip,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
ip_intf.MASTER m_ip,
/*
* AXI DMA Interface
*/
input wire m_dma_axil_awready,
output wire m_dma_axil_awvalid,
output wire [31:0] m_dma_axil_awaddr,
output wire [2:0] m_dma_axil_awprot,
input wire m_dma_axil_wready,
output wire m_dma_axil_wvalid,
output wire [31:0] m_dma_axil_wdata,
output wire [3:0] m_dma_axil_wstrb,
output wire m_dma_axil_bready,
input wire m_dma_axil_bvalid,
input wire [1:0] m_dma_axil_bresp,
input wire m_dma_axil_arready,
output wire m_dma_axil_arvalid,
output wire [31:0] m_dma_axil_araddr,
output wire [2:0] m_dma_axil_arprot,
output wire m_dma_axil_rready,
input wire m_dma_axil_rvalid,
input wire [31:0] m_dma_axil_rdata,
input wire [1:0] m_dma_axil_rresp,
axil_intf.MASTER m_dma_m2s_axi,
axil_intf.MASTER m_dma_s2m_axi
/*
* AXI Ring buffer Interface
*/
input wire m_rb_axil_awready,
output wire m_rb_axil_awvalid,
output wire [31:0] m_rb_axil_awaddr,
output wire [2:0] m_rb_axil_awprot,
input wire m_rb_axil_wready,
output wire m_rb_axil_wvalid,
output wire [31:0] m_rb_axil_wdata,
output wire [3:0] m_rb_axil_wstrb,
output wire m_rb_axil_bready,
input wire m_rb_axil_bvalid,
input wire [1:0] m_rb_axil_bresp,
input wire m_rb_axil_arready,
output wire m_rb_axil_arvalid,
output wire [31:0] m_rb_axil_araddr,
output wire [2:0] m_rb_axil_arprot,
output wire m_rb_axil_rready,
input wire m_rb_axil_rvalid,
input wire [31:0] m_rb_axil_rdata,
input wire [1:0] m_rb_axil_rresp
);
tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in;
@@ -140,209 +66,144 @@ localparam USER_WIDTH = 1;
localparam DEST_WIDTH = 8;
localparam ID_WIDTH = 8;
logic [DATA_WIDTH-1:0] m2s_tx_axis_tdata;
logic [KEEP_WIDTH-1:0] m2s_tx_axis_tkeep;
logic m2s_tx_axis_tvalid;
logic m2s_tx_axis_tready;
logic m2s_tx_axis_tlast;
logic [DEST_WIDTH-1:0] m2s_tx_axis_tdest;
logic [USER_WIDTH-1:0] m2s_tx_axis_tuser;
ip_intf #(.DATA_WIDTH(8)) tcp_tx_ip();
ip_intf #(.DATA_WIDTH(8)) tcp_stream_tx_ip [NUM_TCP]();
ip_intf #(.DATA_WIDTH(8)) tcp_rx_ip [NUM_TCP]();
ip_intf #(.DATA_WIDTH(8)) tcp_stream_rx_ip [NUM_TCP]();
logic [DATA_WIDTH-1:0] s2m_rx_axis_tdata;
logic [KEEP_WIDTH-1:0] s2m_rx_axis_tkeep;
logic s2m_rx_axis_tvalid;
logic s2m_rx_axis_tready;
logic s2m_rx_axis_tlast;
logic [DEST_WIDTH-1:0] s2m_rx_axis_tdest;
logic [USER_WIDTH-1:0] s2m_rx_axis_tuser;
axis_intf #(.DATA_WIDTH(8)) tcp_stream_rx_axis [NUM_TCP]();
logic [NUM_TCP*DATA_WIDTH-1:0] stream_tx_axis_tdata;
logic [NUM_TCP*KEEP_WIDTH-1:0] stream_tx_axis_tkeep;
logic [NUM_TCP-1:0] stream_tx_axis_tvalid;
logic [NUM_TCP-1:0] stream_tx_axis_tready;
logic [NUM_TCP-1:0] stream_tx_axis_tlast;
logic [NUM_TCP*DEST_WIDTH-1:0] stream_tx_axis_tdest;
logic [NUM_TCP*USER_WIDTH-1:0] stream_tx_axis_tuser;
axil_intf m2s_stream_axil[NUM_TCP]();
axil_intf s2m_stream_axil[NUM_TCP]();
logic [NUM_TCP*DATA_WIDTH-1:0] stream_rx_axis_tdata;
logic [NUM_TCP*KEEP_WIDTH-1:0] stream_rx_axis_tkeep;
logic [NUM_TCP-1:0] stream_rx_axis_tvalid;
logic [NUM_TCP-1:0] stream_rx_axis_tready;
logic [NUM_TCP-1:0] stream_rx_axis_tlast;
logic [NUM_TCP*DEST_WIDTH-1:0] stream_rx_axis_tdest;
logic [NUM_TCP*USER_WIDTH-1:0] stream_rx_axis_tuser;
logic [NUM_TCP-1:0] tcp_rx_ip_hdr_valid;
logic [NUM_TCP-1:0] tcp_rx_ip_hdr_ready;
logic [NUM_TCP*48-1:0] tcp_rx_eth_dest_mac;
logic [NUM_TCP*48-1:0] tcp_rx_eth_src_mac;
logic [NUM_TCP*16-1:0] tcp_rx_eth_type;
logic [NUM_TCP*4-1:0] tcp_rx_ip_version;
logic [NUM_TCP*4-1:0] tcp_rx_ip_ihl;
logic [NUM_TCP*6-1:0] tcp_rx_ip_dscp;
logic [NUM_TCP*2-1:0] tcp_rx_ip_ecn;
logic [NUM_TCP*16-1:0] tcp_rx_ip_length;
logic [NUM_TCP*16-1:0] tcp_rx_ip_identification;
logic [NUM_TCP*3-1:0] tcp_rx_ip_flags;
logic [NUM_TCP*13-1:0] tcp_rx_ip_fragment_offset;
logic [NUM_TCP*8-1:0] tcp_rx_ip_ttl;
logic [NUM_TCP*8-1:0] tcp_rx_ip_protocol;
logic [NUM_TCP*16-1:0] tcp_rx_ip_header_checksum;
logic [NUM_TCP*32-1:0] tcp_rx_ip_source_ip;
logic [NUM_TCP*32-1:0] tcp_rx_ip_dest_ip;
logic [NUM_TCP*DATA_WIDTH-1:0] tcp_rx_ip_payload_axis_tdata;
logic [NUM_TCP*KEEP_WIDTH-1:0] tcp_rx_ip_payload_axis_tkeep;
logic [NUM_TCP-1:0] tcp_rx_ip_payload_axis_tvalid;
logic [NUM_TCP-1:0] tcp_rx_ip_payload_axis_tready;
logic [NUM_TCP-1:0] tcp_rx_ip_payload_axis_tlast;
logic [NUM_TCP*ID_WIDTH-1:0] tcp_rx_ip_payload_axis_tid;
logic [NUM_TCP*DEST_WIDTH-1:0] tcp_rx_ip_payload_axis_tdest;
logic [NUM_TCP*USER_WIDTH-1:0] tcp_rx_ip_payload_axis_tuser;
logic [NUM_TCP-1:0] tcp_tx_ip_hdr_valid;
logic [NUM_TCP-1:0] tcp_tx_ip_hdr_ready;
logic [NUM_TCP*6-1:0] tcp_tx_ip_dscp;
logic [NUM_TCP*2-1:0] tcp_tx_ip_ecn;
logic [NUM_TCP*16-1:0] tcp_tx_ip_length;
logic [NUM_TCP*8-1:0] tcp_tx_ip_ttl;
logic [NUM_TCP*8-1:0] tcp_tx_ip_protocol;
logic [NUM_TCP*32-1:0] tcp_tx_ip_source_ip;
logic [NUM_TCP*32-1:0] tcp_tx_ip_dest_ip;
logic [NUM_TCP*DATA_WIDTH-1:0] tcp_tx_ip_payload_axis_tdata;
logic [NUM_TCP-1:0] tcp_tx_ip_payload_axis_tvalid;
logic [NUM_TCP-1:0] tcp_tx_ip_payload_axis_tready;
logic [NUM_TCP-1:0] tcp_tx_ip_payload_axis_tlast;
logic [NUM_TCP*USER_WIDTH-1:0] tcp_tx_ip_payload_axis_tuser;
// ring buffer manager
//m2s dma
// axis demux
axis_demux #(
.M_COUNT(NUM_TCP),
.DATA_WIDTH(DATA_WIDTH),
.DEST_ENABLE(1),
.TDEST_ROUTE(1)
) u_stream_tx_demux (
.clk (i_clk),
.rst (i_rst),
wire [NUM_TCP-1:0] xbar_s_m2s_axi_arvalid;
wire [NUM_TCP-1:0] xbar_s_m2s_axi_arready;
wire [NUM_TCP*32-1:0] xbar_s_m2s_axi_araddr;
wire [NUM_TCP*3-1:0] xbar_s_m2s_axi_arprot;
wire [NUM_TCP-1:0] xbar_s_m2s_axi_rvalid;
wire [NUM_TCP-1:0] xbar_s_m2s_axi_rready;
wire [NUM_TCP*32-1:0] xbar_s_m2s_axi_rdata;
wire [NUM_TCP*2-1:0] xbar_s_m2s_axi_rresp;
.s_axis_tdata (m2s_tx_axis_tdata),
.s_axis_tkeep (m2s_tx_axis_tkeep),
.s_axis_tvalid (m2s_tx_axis_tvalid),
.s_axis_tready (m2s_tx_axis_tready),
.s_axis_tlast (m2s_tx_axis_tlast),
.s_axis_tid ('0),
.s_axis_tdest (m2s_tx_axis_tdest),
.s_axis_tuser (m2s_tx_axis_tuser),
axilxbar #(
.NM(NUM_TCP),
.NS(1),
.SLAVE_ADDR(
{32'h0, 32'hffffffff} // full address space
)
) u_m2s_xbar (
.S_AXI_ACLK (i_clk),
.S_AXI_ARESETN (~i_rst),
.m_axis_tdata (stream_tx_axis_tdata),
.m_axis_tkeep (stream_tx_axis_tkeep),
.m_axis_tvalid (stream_tx_axis_tvalid),
.m_axis_tready (stream_tx_axis_tready),
.m_axis_tlast (stream_tx_axis_tlast),
.m_axis_tid (),
.m_axis_tdest (stream_tx_axis_tdest),
.m_axis_tuser (stream_tx_axis_tuser),
// No write channel
.S_AXI_AWVALID ('0),
.S_AXI_AWREADY (),
.S_AXI_AWADDR ('0),
.S_AXI_AWPROT ('0),
.S_AXI_WVALID ('0),
.S_AXI_WREADY (),
.S_AXI_WDATA ('0),
.S_AXI_WSTRB ('0),
.S_AXI_BVALID (),
.S_AXI_BREADY ('0),
.S_AXI_BRESP (),
.enable ('1),
.drop ('0),
.select ('0) // route selected by tdest
.S_AXI_ARVALID (xbar_s_m2s_axi_arvalid),
.S_AXI_ARREADY (xbar_s_m2s_axi_arready),
.S_AXI_ARADDR (xbar_s_m2s_axi_araddr),
.S_AXI_ARPROT (xbar_s_m2s_axi_arprot),
.S_AXI_RVALID (xbar_s_m2s_axi_rvalid),
.S_AXI_RREADY (xbar_s_m2s_axi_rready),
.S_AXI_RDATA (xbar_s_m2s_axi_rdata),
.S_AXI_RRESP (xbar_s_m2s_axi_rresp),
.M_AXI_AWADDR (),
.M_AXI_AWPROT (),
.M_AXI_AWVALID (),
.M_AXI_AWREADY ('0),
.M_AXI_WDATA (),
.M_AXI_WSTRB (),
.M_AXI_WVALID (),
.M_AXI_WREADY ('0),
.M_AXI_BRESP ('0),
.M_AXI_BVALID ('0),
.M_AXI_BREADY (),
.M_AXI_ARADDR (m_dma_s2m_axi.araddr),
.M_AXI_ARPROT (m_dma_s2m_axi.arprot),
.M_AXI_ARVALID (m_dma_s2m_axi.arvalid),
.M_AXI_ARREADY (m_dma_s2m_axi.arready),
.M_AXI_RDATA (m_dma_s2m_axi.rdata),
.M_AXI_RRESP (m_dma_s2m_axi.rresp),
.M_AXI_RVALID (m_dma_s2m_axi.rvalid),
.M_AXI_RREADY (m_dma_s2m_axi.rready)
);
generate
for (genvar i = 0; i < NUM_TCP; i++) begin
logic req;
logic req_is_wr;
logic [5:0] addr;
logic [31:0] wr_data;
logic [31:0] wr_biten;
assign req = tcp_hwif_out.tcp_streams[i].req;
assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr;
assign addr = tcp_hwif_out.tcp_streams[i].addr;
assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data;
assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten;
assign xbar_s_m2s_axi_arvalid[i] = m2s_stream_axil[i].arvalid;
assign m2s_stream_axil[i].arready = xbar_s_m2s_axi_arready[i];
assign xbar_s_m2s_axi_araddr[32*i+:32] = m2s_stream_axil[i].araddr;
assign xbar_s_m2s_axi_arprot[3*i+:3] = m2s_stream_axil[i].arprot;
assign m2s_stream_axil[i].rvalid = xbar_s_m2s_axi_rvalid[i];
assign xbar_s_m2s_axi_rready[i] = m2s_stream_axil[i].rready;
assign m2s_stream_axil[i].rdata = xbar_s_m2s_axi_rdata[32*i+:32];
assign m2s_stream_axil[i].rresp = xbar_s_m2s_axi_rresp[2*i+:2];
m2s_dma #(
.AXIS_DATA_WIDTH(8)
) u_m2s_dma (
.i_clk (i_clk),
.i_rst (i_rst),
.s_cpuif_req (req),
.s_cpuif_req_is_wr (req_is_wr),
.s_cpuif_addr (addr),
.s_cpuif_wr_data (wr_data),
.s_cpuif_wr_biten (wr_biten),
.s_cpuif_req_stall_wr (),
.s_cpuif_req_stall_rd (),
.s_cpuif_rd_ack (tcp_hwif_in.tcp_streams[i].rd_ack),
.s_cpuif_rd_err (),
.s_cpuif_rd_data (tcp_hwif_in.tcp_streams[i].rd_data),
.s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack),
.s_cpuif_wr_err (),
.m_axil (m2s_stream_axil[i]),
.m_axis (tcp_stream_rx_axis[i])
);
end
endgenerate
//s2m dma
// axis mux
axis_arb_mux #(
.S_COUNT(NUM_TCP),
.DATA_WIDTH(DATA_WIDTH),
.DEST_ENABLE(1)
) u_stream_rx_arb_mux (
.clk (i_clk),
.rst (i_rst),
.s_axis_tdata (stream_rx_axis_tdata),
.s_axis_tkeep (stream_rx_axis_tkeep),
.s_axis_tvalid (stream_rx_axis_tvalid),
.s_axis_tready (stream_rx_axis_tready),
.s_axis_tlast (stream_rx_axis_tlast),
.s_axis_tid ('0),
.s_axis_tdest (stream_rx_axis_tdest),
.s_axis_tuser (stream_rx_axis_tuser),
.m_axis_tdata (s2m_rx_axis_tdata),
.m_axis_tkeep (s2m_rx_axis_tkeep),
.m_axis_tvalid (s2m_rx_axis_tvalid),
.m_axis_tready (s2m_rx_axis_tready),
.m_axis_tlast (s2m_rx_axis_tlast),
.m_axis_tid (),
.m_axis_tdest (s2m_rx_axis_tdest),
.m_axis_tuser (s2m_rx_axis_tuser)
);
// tx_stream arb mux (ip)
ip_arb_mux #(
ip_arb_mux_wrapper #(
.S_COUNT(NUM_TCP),
.DATA_WIDTH(DATA_WIDTH)
) u_tx_stream_arb_mux (
.clk (i_clk),
.rst (i_rst),
.i_clk (i_clk),
.i_rst (i_rst),
.s_ip_hdr_valid (tcp_tx_ip_hdr_valid),
.s_ip_hdr_ready (tcp_tx_ip_hdr_ready),
.s_eth_dest_mac ('0),
.s_eth_src_mac ('0),
.s_eth_type ('0),
.s_ip_version ('0),
.s_ip_ihl ('0),
.s_ip_dscp (tcp_tx_ip_dscp),
.s_ip_ecn (tcp_tx_ip_ecn),
.s_ip_length (tcp_tx_ip_length),
.s_ip_identification ('0),
.s_ip_flags ('0),
.s_ip_fragment_offset ('0),
.s_ip_ttl (tcp_tx_ip_ttl),
.s_ip_protocol (tcp_tx_ip_protocol),
.s_ip_header_checksum ('0),
.s_ip_source_ip (tcp_tx_ip_source_ip),
.s_ip_dest_ip (tcp_tx_ip_dest_ip),
.s_ip_payload_axis_tdata (tcp_tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep ('1),
.s_ip_payload_axis_tvalid (tcp_tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready (tcp_tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast (tcp_tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tid ('0),
.s_ip_payload_axis_tdest ('0),
.s_ip_payload_axis_tuser (tcp_tx_ip_payload_axis_tuser),
.m_ip_hdr_valid (m_ip_hdr_valid),
.m_ip_hdr_ready (m_ip_hdr_ready),
.m_eth_dest_mac (),
.m_eth_src_mac (),
.m_eth_type (),
.m_ip_version (),
.m_ip_ihl (),
.m_ip_dscp (m_ip_dscp),
.m_ip_ecn (m_ip_ecn),
.m_ip_length (m_ip_length),
.m_ip_identification (),
.m_ip_flags (),
.m_ip_fragment_offset (),
.m_ip_ttl (m_ip_ttl),
.m_ip_protocol (m_ip_protocol),
.m_ip_header_checksum (),
.m_ip_source_ip (m_ip_source_ip),
.m_ip_dest_ip (m_ip_dest_ip),
.m_ip_payload_axis_tdata (m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep (),
.m_ip_payload_axis_tvalid (m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready (m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast (m_ip_payload_axis_tlast),
.m_ip_payload_axis_tid (),
.m_ip_payload_axis_tdest (),
.m_ip_payload_axis_tuser (m_ip_payload_axis_tuser)
.s_ip (tcp_stream_tx_ip),
.m_ip (tcp_tx_ip)
);
@@ -382,44 +243,8 @@ generate
.s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack),
.s_cpuif_wr_err (),
.s_ip_hdr_valid (tcp_rx_ip_hdr_valid[i]),
.s_ip_hdr_ready (tcp_rx_ip_hdr_ready[i]),
.s_ip_eth_dest_mac (tcp_rx_eth_dest_mac[i*48+:48]),
.s_ip_eth_src_mac (tcp_rx_eth_src_mac[i*48+:48]),
.s_ip_eth_type (tcp_rx_eth_type[i*16+:16]),
.s_ip_version (tcp_rx_ip_version[i*4+:4]),
.s_ip_ihl (tcp_rx_ip_ihl[i*4+:4]),
.s_ip_dscp (tcp_rx_ip_dscp[i*6+:6]),
.s_ip_ecn (tcp_rx_ip_ecn[i*2+:2]),
.s_ip_length (tcp_rx_ip_length[i*16+:16]),
.s_ip_identification (tcp_rx_ip_identification[i*16+:16]),
.s_ip_flags (tcp_rx_ip_flags[i*3+:3]),
.s_ip_fragment_offset (tcp_rx_ip_fragment_offset[i*13+:13]),
.s_ip_ttl (tcp_rx_ip_ttl[i*8+:8]),
.s_ip_protocol (tcp_rx_ip_protocol[i*8+:8]),
.s_ip_header_checksum (tcp_rx_ip_header_checksum[i*16+:16]),
.s_ip_source_ip (tcp_rx_ip_source_ip[i*32+:32]),
.s_ip_dest_ip (tcp_rx_ip_dest_ip[i*32+:32]),
.s_ip_payload_axis_tdata (tcp_rx_ip_payload_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH]),
.s_ip_payload_axis_tvalid (tcp_rx_ip_payload_axis_tvalid[i*KEEP_WIDTH+:KEEP_WIDTH]),
.s_ip_payload_axis_tready (tcp_rx_ip_payload_axis_tready[i]),
.s_ip_payload_axis_tlast (tcp_rx_ip_payload_axis_tlast[i]),
.s_ip_payload_axis_tuser (tcp_rx_ip_payload_axis_tuser[i*USER_WIDTH+:USER_WIDTH]),
.m_ip_hdr_valid (tcp_tx_ip_hdr_valid),
.m_ip_hdr_ready (tcp_tx_ip_hdr_ready),
.m_ip_dscp (tcp_tx_ip_dscp),
.m_ip_ecn (tcp_tx_ip_ecn),
.m_ip_length (tcp_tx_ip_length),
.m_ip_ttl (tcp_tx_ip_ttl),
.m_ip_protocol (tcp_tx_ip_protocol),
.m_ip_source_ip (tcp_tx_ip_source_ip),
.m_ip_dest_ip (tcp_tx_ip_dest_ip),
.m_ip_payload_axis_tdata (tcp_tx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid (tcp_tx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready (tcp_tx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast (tcp_tx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser (tcp_tx_ip_payload_axis_tuser)
.s_ip_rx (tcp_stream_rx_ip[i]),
.m_ip_tx (tcp_stream_tx_ip[i])
);
end
endgenerate

47
hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
View File

@@ -20,52 +20,11 @@ module tcp_stream #(
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_ip_eth_dest_mac,
input wire [47:0] s_ip_eth_src_mac,
input wire [15:0] s_ip_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser
ip_intf.SLAVE s_ip_rx,
ip_intf.MASTER m_ip_tx
);
// regs
tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in;
tcp_stream_regs_pkg::tcp_stream_regs__out_t hwif_out;

1
hw/super6502_fpga/src/sub/network_processor/sub/verilog-ethernet Submodule

Submodule hw/super6502_fpga/src/sub/network_processor/sub/verilog-ethernet added at 2542187ec9

2
hw/super6502_fpga/src/sub/stream_dmas

Submodule hw/super6502_fpga/src/sub/stream_dmas updated: e65b6c607f...84b9e384ed

2
hw/super6502_fpga/super6502_fpga.xml
View File

@@ -48,8 +48,6 @@
<efx:design_file name="src/sub/network_processor/src/packet_generator.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/ring_buffer_manager.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/eth_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/s2m_dma.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/m2s_dma.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/tcp.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/tx_control.sv" version="default" library="default" />
<efx:design_file name="src/sub/network_processor/src/regs/mac_regs_pkg.sv" version="default" library="default" />