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Add irq code tb

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This commit is contained in:
Byron Lathi
2023-11-18 13:55:29 -08:00
parent 27a0fe5e69
commit dea6227958
9 changed files with 186 additions and 8 deletions
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10
hw/efinix_fpga/simulation/Makefile
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@@ -9,7 +9,8 @@ TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
STANDALONE_TB= interrupt_controller_tb mapper_code_tb mapper_tb
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb
#TODO implement something like sources.list
@@ -32,10 +33,10 @@ full_sim: $(TARGET) $(SD_IMAGE)
vvp -i $(TARGET) -fst
$(STANDALONE_TB): $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
# mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
# iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
$(CODE_TB): $(SRCS) $(TBS) $(INIT_MEM)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
$(TARGET): $(INIT_MEM) $(SRCS)
@@ -58,4 +59,5 @@ clean:
rm -rf $(INIT_MEM)
rm -rf $(SD_IMAGE)
rm -rf $(STANDALONE_TB)
rm -rf $(CODE_TB)
rm -rf *.vcd