New test program

hw/efinix_fpga/debug_profile.wizard.json

@@ -3,7 +3,7 @@
         {
             "name": "la0",
             "type": "la",
-            "uuid": "41ec466b652a438abc3095c20e7f0d30",
+            "uuid": "a6d39fd9db2a421d876dee0a583f9477",
             "trigin_en": false,
             "trigout_en": false,
             "auto_inserted": true,

hw/efinix_fpga/ip/bram/bram_ini.vh

@@ -4,10 +4,10 @@ input integer index;//Mode type
 input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved 
 case (index)
    0: bram_ini_table=
-(val_== 0)?256'h00ea000ea000ea000ea00010000040008d0003a00010000000008d000ff000a9:
-(val_== 1)?256'h01000004000cd0001000000000ad000ea000ea000ea000ea000ea000ea000ea0:
-(val_== 2)?256'hff0008d000f0000a9000f900080000ef000ff0008d00001000a900007000f000:
-(val_== 3)?256'h0000000000000000000000000000000000000000000000000f900080000ef000:
+(val_== 0)?256'h0000000bd00000000a2000f9000d00003a00010000000009d000aa00000000a9:
+(val_== 1)?256'h0000000000000000000000000000000f7000d0000ca000ef000ff0008d000100:
+(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
+(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:
 (val_== 6)?256'h0000000000000000000000000000000000000000000000000000000000000000:

hw/efinix_fpga/ip/bram/init_hex.mem

@@ -1,45 +1,45 @@
 A9
-FF
-8D
+00
+AA
+9D
 00
 10
 3A
-8D
-04
-10
-EA
-EA
-EA
-EA
-EA
-EA
-EA
-EA
-EA
-EA
-EA
-AD
+D0
+F9
+A2
+00
+BD
 00
 10
-CD
-04
-10
-F0
-07
-A9
-01
 8D
 FF
 EF
-80
-F9
-A9
-F0
-8D
-FF
-EF
-80
-F9
+CA
+D0
+F7
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
 00
 00
 00

hw/efinix_fpga/super6502.xml

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Thu December 22 2022 20:21:20" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Thu December 22 2022 20:51:06" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>