First pass at integrating sd controller
This commit is contained in:
Byron Lathi
@@ -0,0 +1,215 @@
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module sd_controller_wrapper(
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input i_clk_100,
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input i_rst_100,
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input logic i_ctrl_AWVALID,
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output logic o_ctrl_AWREADY,
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input logic [31:0] i_ctrl_AWADDR,
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input logic [2:0] i_ctrl_AWPROT,
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input logic i_ctrl_WVALID,
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output logic o_ctrl_WREADY,
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input logic [31:0] i_ctrl_WDATA,
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input logic [3:0] i_ctrl_WSTRB,
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output logic o_ctrl_BVALID,
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input logic i_ctrl_BREADY,
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output logic [1:0] o_ctrl_BRESP,
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input logic i_ctrl_ARVALID,
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output logic o_ctrl_ARREADY,
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input logic [31:0] i_ctrl_ARADDR,
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input logic [2:0] i_ctrl_ARPROT,
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output logic o_ctrl_RVALID,
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input logic i_ctrl_RREADY,
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output logic [31:0] o_ctrl_RDATA,
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output logic [1:0] o_ctrl_RRESP,
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output logic o_dma_AWVALID,
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input logic i_dma_AWREADY,
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output logic [31:0] o_dma_AWADDR,
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output logic [2:0] o_dma_AWPROT,
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output logic o_dma_WVALID,
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input logic i_dma_WREADY,
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output logic [31:0] o_dma_WDATA,
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output logic [31:0] o_dma_WSTRB,
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input logic i_dma_BVALID,
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output logic o_dma_BREADY,
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input logic [1:0] i_dma_BRESP,
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output logic o_dma_ARVALID,
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input logic i_dma_ARREADY,
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output logic [31:0] o_dma_ARADDR,
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output logic [2:0] o_dma_ARPROT,
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input logic i_dma_RVALID,
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output logic o_dma_RREADY,
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input logic [31:0] i_dma_RDATA,
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input logic [1:0] i_dma_RRESP,
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input wire [3:0] sd_dat_dat_i, //Data in from SDcard
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output wire [3:0] sd_dat_out_o, //Data out to SDcard
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output wire sd_dat_oe_o, //SD Card tristate Data Output enable (Connects on the SoC TopLevel)
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input wire sd_cmd_dat_i, //Command in from SDcard
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output wire sd_cmd_out_o, //Command out to SDcard
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output wire sd_cmd_oe_o //SD Card tristate CMD Output enable (Connects on the SoC TopLevel)
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);
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logic wb_reset;
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logic wb_clock;
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logic [31:0] wb_ctrl_data_i;
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logic [31:0] wb_ctrl_data_o;
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logic [31:0] wb_ctrl_addr_i; // need to do address offset either here or in xbar
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logic [3:0] wb_ctrl_sel_i;
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logic wb_ctrl_we_i;
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logic wb_ctrl_cyc_i;
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logic wb_ctrl_stb_i;
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logic wb_ctrl_ack_o;
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logic [31:0] wb_dma_adr_o;
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logic [3:0] wb_dma_sel_o;
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logic wb_dma_we_o;
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logic [31:0] wb_dma_dat_i;
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logic [31:0] wb_dma_dat_o;
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logic wb_dma_cyc_o;
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logic wb_dma_stb_o;
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logic wb_dma_ack_i;
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logic [2:0] wb_dma_cti_o;
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logic [1:0] wb_dma_bte_o;
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//axilite2wbsp
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axilite2wbsp #(
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.C_AXI_DATA_WIDTH(32),
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.C_AXI_ADDR_WIDTH(32),
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.LGFIFO(4),
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.OPT_READONLY(0),
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.OPT_WRITEONLY(0)
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) u_axilite2wbsp (
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.i_clk (i_clk_100),
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.i_axi_reset_n (~i_rst_100),
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.i_axi_awvalid (i_ctrl_AWVALID),
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.o_axi_awready (o_ctrl_AWREADY),
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.i_axi_awaddr (i_ctrl_AWADDR),
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.i_axi_awprot (i_ctrl_AWPROT),
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.i_axi_wvalid (i_ctrl_AWVALID),
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.o_axi_wready (o_ctrl_WREADY),
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.i_axi_wdata (i_ctrl_WDATA),
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.i_axi_wstrb (i_ctrl_WSTRB),
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.o_axi_bvalid (o_ctrl_BVALID),
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.i_axi_bready (i_ctrl_BREADY),
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.o_axi_bresp (o_ctrl_BRESP),
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.i_axi_arvalid (i_ctrl_ARVALID),
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.o_axi_arready (o_ctrl_ARREADY),
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.i_axi_araddr (i_ctrl_ARADDR),
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.i_axi_arprot (i_ctrl_ARPROT),
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.o_axi_rvalid (o_ctrl_RVALID),
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.i_axi_rready (i_ctrl_RREADY),
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.o_axi_rdata (o_ctrl_rdata),
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.o_axi_rresp (o_ctrl_rresp),
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.o_reset (wb_reset),
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.o_wb_cyc (wb_ctrl_cyc_i),
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.o_wb_stb (wb_ctrl_stb_i),
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.o_wb_we (wb_ctrl_we_i),
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.o_wb_addr (wb_ctrl_addr_i),
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.o_wb_data (wb_ctrl_data_i),
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.o_wb_sel (wb_ctrl_sel_i),
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.i_wb_stall ('0),
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.i_wb_ack (wb_ctrl_ack_o),
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.i_wb_data (wb_ctrl_data_o),
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.i_wb_err ('0)
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);
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//wb2axilite
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wbm2axilite #(
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.C_AXI_ADDR_WIDTH(32)
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) u_wbm2axilite (
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.i_clk (i_clk_100),
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.i_reset (wb_reset),
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.i_wb_cyc (wb_dma_cyc_o),
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.i_wb_stb (wb_dma_stb_o),
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.i_wb_we (wb_dma_we_o),
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.i_wb_addr (wb_dma_adr_o),
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.i_wb_data (wb_dma_dat_o),
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.i_wb_sel (wb_dma_sel_o),
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.o_wb_stall (),
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.o_wb_ack (wb_dma_ack_i),
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.o_wb_data (wb_dma_dat_i),
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.o_wb_err (),
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.o_axi_awvalid (o_dma_AWVALID),
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.i_axi_awready (i_dma_AWREADY),
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.o_axi_awaddr (o_dma_AWADDR),
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.o_axi_awprot (o_dma_AWPROT),
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.o_axi_wvalid (o_dma_WVALID),
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.i_axi_wready (i_dma_WREADY),
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.o_axi_wdata (o_dma_WDATA),
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.o_axi_wstrb (o_dma_WSTRB),
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.i_axi_bvalid (i_dma_BVALID),
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.o_axi_bready (o_dma_BREADY),
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.i_axi_bresp (i_dma_BRESP),
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.o_axi_arvalid (o_dma_ARVALID),
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.i_axi_arready (i_dma_ARREADY),
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.o_axi_araddr (o_dma_ARADDR),
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.o_axi_arprot (o_dma_ARPROT),
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.i_axi_rvalid (i_dma_RVALID),
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.o_axi_rready (o_dma_RREADY),
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.i_axi_rdata (i_dma_RDATA),
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.i_axi_rresp (i_dma_RRESP)
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);
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//sdc controller
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sdc_controller u_sdc_controller (
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.wb_clk_i (i_clk_100),
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.wb_rst_i (wb_reset),
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.wb_dat_i (wb_ctrl_data_i),
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.wb_dat_o (wb_ctrl_data_o),
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.wb_adr_i (wb_ctrl_addr_i),
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.wb_sel_i (wb_ctrl_sel_i),
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.wb_we_i (wb_ctrl_we_i),
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.wb_cyc_i (wb_ctrl_cyc_i),
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.wb_stb_i (wb_ctrl_stb_i),
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.wb_ack_o (wb_ctrl_ack_o),
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.m_wb_adr_o (wb_dma_adr_o),
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.m_wb_sel_o (wb_dma_sel_o),
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.m_wb_we_o (wb_dma_we_o),
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.m_wb_dat_o (wb_dma_dat_o),
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.m_wb_dat_i (wb_dma_dat_i),
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.m_wb_cyc_o (wb_dma_cyc_o),
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.m_wb_stb_o (wb_dma_stb_o),
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.m_wb_ack_i (wb_dma_ack_i),
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.m_wb_cti_o (), // uhh, guys?
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.m_wb_bte_o (),
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.sd_cmd_dat_i (sd_cmd_i),
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.sd_cmd_dat_o (sd_cmd_o),
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.sd_cmd_oe_o (sd_cmd_oe),
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.sd_dat_dat_i (sd_dat_i),
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.sd_dat_dat_o (sd_dat_o),
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.sd_dat_oe_o (sd_dat_oe),
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.card_detect (sd_cd),
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.sd_clk_o_pad (sd_clk)
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);
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endmodule
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@@ -1,4 +1,4 @@
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<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Tue Jul 16 2024 12:02:55 AM" location="/cluster/projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Tue Jul 16 2024 06:55:10 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion" />
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<efx:device name="T20F256" />
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@@ -18,6 +18,25 @@
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<efx:design_file name="src/sub/axi_crossbar/src/rtl/rr_scheduler.sv" version="default" library="default" />
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<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default" />
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<efx:design_file name="src/sub/rtl-common/src/rtl/async_fifo.sv" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_controller_wrapper.sv" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sdc_controller.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_cmd_master.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_crc_7.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_controller_wb.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_fifo_rx_filler.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_rx_fifo.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_cmd_serial_host.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_fifo_tx_filler.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_data_serial_host.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_data_master.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_rx_fifo_tb.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_bd.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_defines.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_tx_fifo.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_clock_divider.v" version="default" library="default" />
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<efx:design_file name="src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller/rtl/sdc_dma/verilog/sd_crc_16.v" version="default" library="default" />
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<efx:design_file name="src/sub/wb2axip/rtl/axlite2wbsp.v" version="default" library="default" />
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<efx:design_file name="src/sub/wb2axip/rtl/wbm2axilite.v" version="default" library="default" />
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<efx:top_vhdl_arch name="" />
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</efx:design_info>
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<efx:constraint_info>
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