From e0e20d7fb40344cfbfe934052dfeed92df51db18 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 15 Oct 2023 13:37:13 -0700
Subject: [PATCH] Add indirect test

---
 sw/test_code/indirect_test/Makefile  | 39 ++++++++++++++++++++++++++++
 sw/test_code/indirect_test/link.ld   | 35 +++++++++++++++++++++++++
 sw/test_code/indirect_test/main.s    | 20 ++++++++++++++
 sw/test_code/indirect_test/vectors.s | 14 ++++++++++
 4 files changed, 108 insertions(+)
 create mode 100644 sw/test_code/indirect_test/Makefile
 create mode 100644 sw/test_code/indirect_test/link.ld
 create mode 100644 sw/test_code/indirect_test/main.s
 create mode 100644 sw/test_code/indirect_test/vectors.s

diff --git a/sw/test_code/indirect_test/Makefile b/sw/test_code/indirect_test/Makefile
new file mode 100644
index 0000000..5fbaadc
--- /dev/null
+++ b/sw/test_code/indirect_test/Makefile
@@ -0,0 +1,39 @@
+CC=../../cc65/bin/cl65
+LD=../../cc65/bin/cl65
+CFLAGS=-T -t none -I. --cpu "65C02"
+LDFLAGS=-C link.ld -m $(NAME).map
+
+NAME=indirect_test
+
+BIN=$(NAME).bin
+HEX=$(NAME).hex
+
+LISTS=lists
+
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
+OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
+OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
+
+# Make sure the kernel linked to correct address, no relocation!
+all: $(HEX)
+
+$(HEX): $(BIN)
+	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
+
+$(BIN): $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+%.o: %.c $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+%.o: %.s $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+$(LISTS):
+	mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
+
+.PHONY: clean
+clean:
+	rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
+
diff --git a/sw/test_code/indirect_test/link.ld b/sw/test_code/indirect_test/link.ld
new file mode 100644
index 0000000..66a42fe
--- /dev/null
+++ b/sw/test_code/indirect_test/link.ld
@@ -0,0 +1,35 @@
+MEMORY
+{
+  ZP:  start = $0,    size = $100,  type = rw, define = yes;
+  SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
+  ROM: start = $F000, size = $1000, file = %O;
+}
+
+SEGMENTS {
+    ZEROPAGE: load = ZP,  type = zp,  define   = yes;
+    DATA:     load = ROM, type = rw,  define   = yes, run = SDRAM;
+    BSS:      load = SDRAM, type = bss, define   = yes;
+    HEAP:     load = SDRAM, type = bss, optional = yes;
+    STARTUP:  load = ROM, type = ro;
+    ONCE:     load = ROM, type = ro,  optional = yes;
+    CODE:     load = ROM, type = ro;
+    RODATA:   load = ROM, type = ro;
+    VECTORS:  load = ROM, type = ro,  start    = $FFFA;
+}
+
+FEATURES {
+    CONDES:    segment = STARTUP,
+               type    = constructor,
+               label   = __CONSTRUCTOR_TABLE__,
+               count   = __CONSTRUCTOR_COUNT__;
+    CONDES:    segment = STARTUP,
+               type    = destructor,
+               label   = __DESTRUCTOR_TABLE__,
+               count   = __DESTRUCTOR_COUNT__;
+}
+
+SYMBOLS {
+    # Define the stack size for the application
+    __STACKSIZE__:  value = $0200, type = weak;
+    __STACKSTART__: type = weak, value = $0800; # 2k stack
+}
diff --git a/sw/test_code/indirect_test/main.s b/sw/test_code/indirect_test/main.s
new file mode 100644
index 0000000..65cf841
--- /dev/null
+++ b/sw/test_code/indirect_test/main.s
@@ -0,0 +1,20 @@
+.export _init, _nmi_int, _irq_int
+
+.code
+
+_nmi_int:
+_irq_int:
+
+_init:
+    ldx #$ff
+    txs
+
+    lda #$aa
+    sta $01
+    lda #$bb
+    sta $00
+    ldy #$1
+    lda #$cc
+    sta ($00),y
+
+@end:   bra @end
\ No newline at end of file
diff --git a/sw/test_code/indirect_test/vectors.s b/sw/test_code/indirect_test/vectors.s
new file mode 100644
index 0000000..81ae6e0
--- /dev/null
+++ b/sw/test_code/indirect_test/vectors.s
@@ -0,0 +1,14 @@
+; ---------------------------------------------------------------------------
+; vectors.s
+; ---------------------------------------------------------------------------
+;
+; Defines the interrupt vector table.
+
+.import    _init
+.import    _nmi_int, _irq_int
+
+.segment  "VECTORS"
+
+.addr      _nmi_int    ; NMI vector
+.addr      _init       ; Reset vector
+.addr      _irq_int    ; IRQ/BRK vector
\ No newline at end of file