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Add some flops to the mapper

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This is NOT how to do CDC
This commit is contained in:
Byron Lathi
2023-11-30 17:40:21 -08:00
parent db4848b6fe
commit e805b19eca
4 changed files with 109 additions and 90 deletions
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15
hw/efinix_fpga/constraints/super6502.pt.sdc
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@@ -11,11 +11,18 @@
# PLL Constraints
#################
create_clock -period 5.0000 i_sdrclk
create_clock -period 5.0000 i_tACclk
create_clock -period 10.0000 i_sysclk
create_clock -period 20.0000 clk_50
create_clock -period 500.0000 clk_2
create_generated_clock -source clk_50 -multiply_by 4 i_sdrclk
create_generated_clock -source clk_50 -multiply_by 4 i_tACclk
create_generated_clock -source clk_50 -multiply_by 2 i_sysclk
create_generated_clock -source clk_50 -divide_by 25 clk_cpu
# create_clock -period 5.0000 i_sdrclk
# create_clock -period 5.0000 i_tACclk
# create_clock -period 10.0000 i_sysclk
# create_clock -period 500.0000 clk_cpu
# GPIO Constraints
####################