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Add some flops to the mapper

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This is NOT how to do CDC
This commit is contained in:
Byron Lathi
2023-11-30 17:40:21 -08:00
parent db4848b6fe
commit e805b19eca
4 changed files with 109 additions and 90 deletions
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15
hw/efinix_fpga/constraints/super6502.pt.sdc
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@@ -11,11 +11,18 @@
# PLL Constraints
#################
create_clock -period 5.0000 i_sdrclk
create_clock -period 5.0000 i_tACclk
create_clock -period 10.0000 i_sysclk
create_clock -period 20.0000 clk_50
create_clock -period 500.0000 clk_2
create_generated_clock -source clk_50 -multiply_by 4 i_sdrclk
create_generated_clock -source clk_50 -multiply_by 4 i_tACclk
create_generated_clock -source clk_50 -multiply_by 2 i_sysclk
create_generated_clock -source clk_50 -divide_by 25 clk_cpu
# create_clock -period 5.0000 i_sdrclk
# create_clock -period 5.0000 i_tACclk
# create_clock -period 10.0000 i_sysclk
# create_clock -period 500.0000 clk_cpu
# GPIO Constraints
####################

11
hw/efinix_fpga/src/mapper.sv
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@@ -1,6 +1,8 @@
module mapper(
input i_reset,
input i_clk,
input i_clk50,
input i_clk100,
input i_cs,
input i_we,
input [7:0] i_data,
@@ -10,6 +12,7 @@ module mapper(
);
logic [15:0] mm [16];
logic [15:0] _mm [16];
logic [15:0] mm_next [16];
logic [31:0] we;
@@ -20,13 +23,14 @@ logic [15:0] mm_sel;
logic [15:0] selected_mm;
logic [15:0] _cpu_addr;
always_comb begin
we = ((i_we & i_cs) << i_cpu_addr[4:0]);
mm_sel = (1 << i_cpu_addr[4:1]);
o_data = mm_sel[8*i_cpu_addr[0] +: 8];
selected_mm = mm[i_cpu_addr[15:12]];
o_mapped_addr = {selected_mm[12:0], i_cpu_addr[11:0]};
for (int i = 0; i < 16; i++) begin
@@ -40,6 +44,11 @@ always_comb begin
end
end
always_ff @(posedge i_clk100) begin
_cpu_addr <= i_cpu_addr;
selected_mm <= mm[_cpu_addr[15:12]];
end
always_ff @(negedge i_clk or posedge i_reset) begin
if (i_reset) begin
for (int i = 0; i < 16; i++) begin

2
hw/efinix_fpga/src/super6502.sv
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@@ -202,6 +202,8 @@ timer u_timer(
mapper u_mapper(
.i_reset(~cpu_resb),
.i_clk(clk_cpu),
.i_clk50(clk_50),
.i_clk100(i_sysclk),
.i_cs(w_mapper_cs),
.i_we(~cpu_rwb),
.i_data(cpu_data_in),

3
hw/efinix_fpga/super6502.xml
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@@ -1,4 +1,5 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Fri Nov 24 2023 17:49:43" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Thu November 30 2023 17:33:58" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>