From ee97c4cbaa4b01e23fd6e86b074a09cd4cf9c8b9 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 17 Mar 2022 14:25:26 -0500
Subject: [PATCH] Add platform generation to build stage

---
 .gitlab-ci.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 4998610..16e5ba1 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -15,6 +15,7 @@ build-fpga:
   image: bslathi19/modelsim_18.1:lite
   script:
     - cd hw/fpga/
+    - qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G
     - quartus_map super6502 -c super6502
 
 test_addr_decode: