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Update SD stuff

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This commit is contained in:
Byron Lathi
2024-07-20 15:58:33 -07:00
parent bdb3fc96d6
commit f126e383a3
7 changed files with 136 additions and 25 deletions
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2
Makefile
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@@ -28,6 +28,8 @@ $(CC65):
$(INIT_HEX): $(CC65) script/generate_rom_image.py $(HEX) $(INIT_HEX): $(CC65) script/generate_rom_image.py $(HEX)
python script/generate_rom_image.py -i $(HEX) -o $@ python script/generate_rom_image.py -i $(HEX) -o $@
# This should get dependencies of rom, not be phony
.PHONY: $(HEX)
$(HEX): $(HEX):
$(MAKE) -C sw/$(ROM_TARGET) $(notdir $@) $(MAKE) -C sw/$(ROM_TARGET) $(notdir $@)

1
hw/super6502_fpga/sources.list
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@@ -7,6 +7,7 @@ src/sub/rtl-common/src/rtl/ff_cdc.sv
src/sub/rtl-common/src/rtl/shallow_async_fifo.sv src/sub/rtl-common/src/rtl/shallow_async_fifo.sv
src/sub/rtl-common/src/rtl/sync_fifo.sv src/sub/rtl-common/src/rtl/sync_fifo.sv
src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv
src/sub/rtl-common/src/rtl/shadow_regs.sv
ip/sdram_controller/sdram_controller.v ip/sdram_controller/sdram_controller.v
src/sub/wb2axip/rtl/axilxbar.v src/sub/wb2axip/rtl/axilxbar.v
src/sub/wb2axip/rtl/addrdecode.v src/sub/wb2axip/rtl/addrdecode.v

2
hw/super6502_fpga/src/sim/Makefile
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@@ -20,6 +20,8 @@ waves: $(TB_NAME)
$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../ iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
# I feel like this should also realize that the outside files are newer...
.PHONY: $(COPY_FILES)
$(COPY_FILES): ../../$@ $(COPY_FILES): ../../$@
cp ../../$@ . cp ../../$@ .

2
hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: 6bb56be03a...96bf398cf4

96
hw/super6502_fpga/src/sub/sd_controller_wrapper/sd_controller_wrapper.sv
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@@ -66,6 +66,64 @@ module sd_controller_wrapper #(
output wire o_int output wire o_int
); );
logic shadow_AXI_AWVALID;
logic shadow_AXI_AWREADY;
logic [31:0] shadow_AXI_AWADDR;
logic shadow_AXI_WVALID;
logic shadow_AXI_WREADY;
logic [31:0] shadow_AXI_WDATA;
logic [3:0] shadow_AXI_WSTRB;
logic shadow_AXI_BVALID;
logic shadow_AXI_BREADY;
logic [1:0] shadow_AXI_BRESP;
logic shadow_AXI_ARVALID;
logic shadow_AXI_ARREADY;
logic [31:0] shadow_AXI_ARADDR;
logic shadow_AXI_RVALID;
logic shadow_AXI_RREADY;
logic [31:0] shadow_AXI_RDATA;
logic [1:0] shadow_AXI_RRESP;
shadow_regs #(.N(8)) u_shadow_regs (
.i_clk (i_clk),
.i_reset (i_reset),
.S_AXIL_AWVALID (S_AXIL_AWVALID),
.S_AXIL_AWREADY (S_AXIL_AWREADY),
.S_AXIL_AWADDR (S_AXIL_AWADDR-BASE_ADDRESS),
.S_AXIL_WVALID (S_AXIL_WVALID),
.S_AXIL_WREADY (S_AXIL_WREADY),
.S_AXIL_WDATA (S_AXIL_WDATA),
.S_AXIL_WSTRB (S_AXIL_WSTRB),
.S_AXIL_BVALID (S_AXIL_BVALID),
.S_AXIL_BREADY (S_AXIL_BREADY),
.S_AXIL_BRESP (S_AXIL_BRESP),
.S_AXIL_ARVALID (S_AXIL_ARVALID),
.S_AXIL_ARREADY (S_AXIL_ARREADY),
.S_AXIL_ARADDR (S_AXIL_ARADDR-BASE_ADDRESS),
.S_AXIL_RVALID (S_AXIL_RVALID),
.S_AXIL_RREADY (S_AXIL_RREADY),
.S_AXIL_RDATA (S_AXIL_RDATA),
.S_AXIL_RRESP (S_AXIL_RRESP),
.M_AXI_AWVALID (shadow_AXI_AWVALID),
.M_AXI_AWREADY (shadow_AXI_AWREADY),
.M_AXI_AWADDR (shadow_AXI_AWADDR),
.M_AXI_WVALID (shadow_AXI_WVALID),
.M_AXI_WREADY (shadow_AXI_WREADY),
.M_AXI_WDATA (shadow_AXI_WDATA),
.M_AXI_WSTRB (shadow_AXI_WSTRB),
.M_AXI_BVALID (shadow_AXI_BVALID),
.M_AXI_BREADY (shadow_AXI_BREADY),
.M_AXI_BRESP (shadow_AXI_BRESP),
.M_AXI_ARVALID (shadow_AXI_ARVALID),
.M_AXI_ARREADY (shadow_AXI_ARREADY),
.M_AXI_ARADDR (shadow_AXI_ARADDR),
.M_AXI_RVALID (shadow_AXI_RVALID),
.M_AXI_RREADY (shadow_AXI_RREADY),
.M_AXI_RDATA (shadow_AXI_RDATA),
.M_AXI_RRESP (shadow_AXI_RRESP)
);
sdio_top #( sdio_top #(
@@ -82,25 +140,25 @@ sdio_top #(
.i_reset (i_reset), .i_reset (i_reset),
.i_hsclk ('0), // Not using serdes .i_hsclk ('0), // Not using serdes
.S_AXIL_AWVALID (S_AXIL_AWVALID), .S_AXIL_AWVALID (shadow_AXI_AWVALID),
.S_AXIL_AWREADY (S_AXIL_AWREADY), .S_AXIL_AWREADY (shadow_AXI_AWREADY),
.S_AXIL_AWADDR (S_AXIL_AWADDR-BASE_ADDRESS), .S_AXIL_AWADDR (shadow_AXI_AWADDR),
.S_AXIL_AWPROT ('0), .S_AXIL_AWPROT (),
.S_AXIL_WVALID (S_AXIL_WVALID), .S_AXIL_WVALID (shadow_AXI_WVALID),
.S_AXIL_WREADY (S_AXIL_WREADY), .S_AXIL_WREADY (shadow_AXI_WREADY),
.S_AXIL_WDATA (S_AXIL_WDATA), .S_AXIL_WDATA (shadow_AXI_WDATA),
.S_AXIL_WSTRB (S_AXIL_WSTRB), .S_AXIL_WSTRB (shadow_AXI_WSTRB),
.S_AXIL_BVALID (S_AXIL_BVALID), .S_AXIL_BVALID (shadow_AXI_BVALID),
.S_AXIL_BREADY (S_AXIL_BREADY), .S_AXIL_BREADY (shadow_AXI_BREADY),
.S_AXIL_BRESP (S_AXIL_BRESP), .S_AXIL_BRESP (shadow_AXI_BRESP),
.S_AXIL_ARVALID (S_AXIL_ARVALID), .S_AXIL_ARVALID (shadow_AXI_ARVALID),
.S_AXIL_ARREADY (S_AXIL_ARREADY), .S_AXIL_ARREADY (shadow_AXI_ARREADY),
.S_AXIL_ARADDR (S_AXIL_ARADDR-BASE_ADDRESS), .S_AXIL_ARADDR (shadow_AXI_ARADDR),
.S_AXIL_ARPROT ('0), .S_AXIL_ARPROT (),
.S_AXIL_RVALID (S_AXIL_RVALID), .S_AXIL_RVALID (shadow_AXI_RVALID),
.S_AXIL_RREADY (S_AXIL_RREADY), .S_AXIL_RREADY (shadow_AXI_RREADY),
.S_AXIL_RDATA (S_AXIL_RDATA), .S_AXIL_RDATA (shadow_AXI_RDATA),
.S_AXIL_RRESP (S_AXIL_RRESP), .S_AXIL_RRESP (shadow_AXI_RRESP),
.M_AXI_AWVALID (M_AXI_AWVALID), .M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY), .M_AXI_AWREADY (M_AXI_AWREADY),

3
hw/super6502_fpga/super6502_fpga.xml
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@@ -1,4 +1,4 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Wed Jul 17 2024 09:07:23 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd"> <efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sat Jul 20 2024 04:02:27 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info> <efx:device_info>
<efx:family name="Trion" /> <efx:family name="Trion" />
<efx:device name="T20F256" /> <efx:device name="T20F256" />
@@ -13,6 +13,7 @@
<efx:design_file name="src/sub/rtl-common/src/rtl/ff_cdc.sv" version="default" library="default" /> <efx:design_file name="src/sub/rtl-common/src/rtl/ff_cdc.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default" /> <efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/async_fifo.sv" version="default" library="default" /> <efx:design_file name="src/sub/rtl-common/src/rtl/async_fifo.sv" version="default" library="default" />
<efx:design_file name="src/sub/rtl-common/src/rtl/shadow_regs.sv" version="default" library="default" />
<efx:design_file name="src/sub/wb2axip/rtl/axilxbar.v" version="default" library="default" /> <efx:design_file name="src/sub/wb2axip/rtl/axilxbar.v" version="default" library="default" />
<efx:design_file name="src/sub/wb2axip/rtl/addrdecode.v" version="default" library="default" /> <efx:design_file name="src/sub/wb2axip/rtl/addrdecode.v" version="default" library="default" />
<efx:design_file name="src/sub/wb2axip/rtl/skidbuffer.v" version="default" library="default" /> <efx:design_file name="src/sub/wb2axip/rtl/skidbuffer.v" version="default" library="default" />

53
sw/test_code/sd_controller_test/main.s
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@@ -7,15 +7,27 @@
.addr _irq_int ; IRQ/BRK vector .addr _irq_int ; IRQ/BRK vector
SD_CONTROLLER = $e000 SD_CONTROLLER = $e000
SD_CMD = SD_CONTROLLER SD_CMD = SD_CONTROLLER
SD_ARG = SD_CONTROLLER + $4 SD_ARG = SD_CONTROLLER + $4
SD_FIFO_0 = SD_CONTROLLER + $8 SD_FIFO_0 = SD_CONTROLLER + $8
SD_FIFO_2 = SD_CONTROLLER + $C SD_FIFO_2 = SD_CONTROLLER + $C
SD_PHY = SD_CONTROLLER + $10 SD_PHY = SD_CONTROLLER + $10
SD_PHY_CLKDIV = SD_PHY
SD_PHY_CLKCTRL = SD_PHY + $1
SD_PHY_SAMP_VOLT = SD_PHY + $2
SD_PHY_BLKSIZ = SD_PHY + $3
SD_DMA_BASE = SD_CONTROLLER + $28 SD_DMA_BASE = SD_CONTROLLER + $28
SD_DMA_STAT_CTRL = SD_CONTROLLER + $2C SD_DMA_STAT_CTRL = SD_CONTROLLER + $2C
SDIOCLK_100KHZ = $FC
SPEED_512B = $09
.zeropage .zeropage
rca: .res 4 rca: .res 4
@@ -25,7 +37,42 @@ _nmi_int:
_irq_int: _irq_int:
_init: _init:
ldx #$ff ldx #$ff
txs txs
@end: bra @end stz SD_PHY_CLKCTRL
stz SD_PHY_SAMP_VOLT
lda #SPEED_512B
sta SD_PHY_BLKSIZ
lda #SDIOCLK_100KHZ
sta SD_PHY_CLKDIV
@wait_clk: lda SD_PHY_CLKDIV
cmp #SDIOCLK_100KHZ
bne @wait_clk
stz SD_CMD+$3
lda #$04
sta SD_CMD+$2
lda #$08
sta SD_CMD+$1
lda #$40
sta SD_CMD
jsr wait_busy
lda #$01
sta SD_CMD+$1
lda #$48
sta SD_CMD
jsr wait_busy
@end:
bra @end
wait_busy: lda SD_CMD+$1
bit #$40
bne wait_busy
rts