bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Done for the day

Browse Source
This commit is contained in:
Byron Lathi
2024-08-19 22:59:12 -07:00
parent 752fce5b2e
commit f492c5b23d
7 changed files with 843 additions and 193 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
View File

@@ -43,8 +43,26 @@ module super6502_fpga(
input i_sd_dat,
output o_sd_dat,
output o_sd_dat_oe,
output o_sd_clk
// input i_sd_cd
output o_sd_clk,
// input i_sd_cd,
//MII Interface
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
// MDIO Interface
input i_Mdi,
output o_Mdo,
output o_MdoEn,
output o_Mdc,
output phy_rstn
);

2
hw/super6502_fpga/src/sim/Makefile
View File

@@ -9,7 +9,7 @@ SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
INCLUDE=include/sdram_controller_define.vh
TB_NAME=sim_top
TB_NAME=./obj_dir/Vsim_top
COPY_FILES=addr_map.mem init_hex.mem
SD_IMAGE=sd_image.bin

1
hw/super6502_fpga/src/sub/network_processor/sources.list
View File

@@ -10,3 +10,4 @@ src/network_processor.sv
src/tcp_state_manager.sv
src/tcp_stream.sv
src/tcp.sv
src/eth_wrapper.sv

150
hw/super6502_fpga/src/sub/network_processor/src/eth_wrapper.sv Normal file
View File

@@ -0,0 +1,150 @@
module eth_wrapper #(
parameter MAC_DATA_WIDTH=8,
parameter MAC_KEEP_WIDTH = ((MAC_DATA_WIDTH+7)/8)
)(
input wire rst,
input wire clk_sys,
/*
* AXI input
*/
input wire [MAC_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [MAC_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [MAC_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [MAC_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* MII interface
*/
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
/*
* CPUIF interface
*/
input wire s_cpuif_req,
input wire s_cpuif_req_is_wr,
input wire [4:0] s_cpuif_addr,
input wire [31:0] s_cpuif_wr_data,
input wire [31:0] s_cpuif_wr_biten,
output wire s_cpuif_req_stall_wr,
output wire s_cpuif_req_stall_rd,
output wire s_cpuif_rd_ack,
output wire s_cpuif_rd_err,
output wire [31:0] s_cpuif_rd_data,
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err,
// MDIO Interface
input wire Mdi,
output wire Mdo,
output wire MdoEn,
output wire Mdc,
output wire phy_rstn
);
assign Mdo = '0;
assign MdoEn = '0;
assign Mdc = '0;
mac_regs_pkg::mac_regs__in_t hwif_in;
mac_regs_pkg::mac_regs__out_t hwif_out;
mac_regs u_mac_regs(
.clk(clk_sys),
.rst(rst),
.s_cpuif_req (s_cpuif_req),
.s_cpuif_req_is_wr (s_cpuif_req_is_wr),
.s_cpuif_addr (s_cpuif_addr),
.s_cpuif_wr_data (s_cpuif_wr_data),
.s_cpuif_wr_biten (s_cpuif_wr_biten),
.s_cpuif_req_stall_wr (s_cpuif_req_stall_wr),
.s_cpuif_req_stall_rd (s_cpuif_req_stall_rd),
.s_cpuif_rd_ack (s_cpuif_rd_ack),
.s_cpuif_rd_err (s_cpuif_rd_err),
.s_cpuif_rd_data (s_cpuif_rd_data),
.s_cpuif_wr_ack (s_cpuif_wr_ack),
.s_cpuif_wr_err (s_cpuif_wr_err),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
);
assign phy_rstn = hwif_out.ctrl.phy_rstn.value;
eth_mac_mii_fifo #(
.TARGET("GENERIC"),
.AXIS_DATA_WIDTH(MAC_DATA_WIDTH),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FIFO_RAM_PIPELINE(1),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FIFO_RAM_PIPELINE(1),
.RX_FRAME_FIFO(1)
) u_mac (
.rst (reset),
.logic_clk (clk_100),
.logic_rst (reset),
.tx_axis_tdata (tx_axis_tdata),
.tx_axis_tkeep (tx_axis_tkeep),
.tx_axis_tvalid (tx_axis_tvalid),
.tx_axis_tready (tx_axis_tready),
.tx_axis_tlast (tx_axis_tlast),
.tx_axis_tuser ('0),
.rx_axis_tdata (rx_axis_tdata),
.rx_axis_tkeep (rx_axis_tkeep),
.rx_axis_tvalid (rx_axis_tvalid),
.rx_axis_tready (rx_axis_tready),
.rx_axis_tlast (rx_axis_tlast),
.rx_axis_tuser (rx_axis_tuser),
.mii_rx_clk (mii_rx_clk),
.mii_rxd (mii_rxd_mux),
.mii_rx_dv (mii_rx_dv_mux),
.mii_rx_er (mii_rx_er_mux),
.mii_tx_clk (mii_tx_clk),
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.tx_error_underflow (hwif_in.stats.tx_error_underflow.hwset),
.tx_fifo_overflow (hwif_in.stats.tx_fifo_overflow.hwset),
.tx_fifo_bad_frame (hwif_in.stats.tx_fifo_bad_frame.hwset),
.tx_fifo_good_frame (hwif_in.stats.tx_fifo_good_frame.hwset),
.rx_error_bad_frame (hwif_in.stats.rx_error_bad_frame.hwset),
.rx_error_bad_fcs (hwif_in.stats.rx_error_bad_fcs.hwset),
.rx_fifo_overflow (hwif_in.stats.rx_fifo_overflow.hwset),
.rx_fifo_bad_frame (hwif_in.stats.rx_fifo_bad_frame.hwset),
.rx_fifo_good_frame (hwif_in.stats.rx_fifo_good_frame.hwset),
.cfg_ifg (hwif_out.ctrl.ifg.value),
.cfg_tx_enable (hwif_out.ctrl.tx_en.value), // this should be configurable w/ regfile
.cfg_rx_enable (hwif_out.ctrl.rx_en.value)
);
endmodule

558
hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv
View File

@@ -4,57 +4,527 @@ module network_processor #(
input i_clk,
input i_rst,
output logic s_reg_axil_awready,
input wire s_reg_axil_awvalid,
input wire [8:0] s_reg_axil_awaddr,
input wire [2:0] s_reg_axil_awprot,
output logic s_reg_axil_wready,
input wire s_reg_axil_wvalid,
input wire [31:0] s_reg_axil_wdata,
input wire [3:0] s_reg_axil_wstrb,
input wire s_reg_axil_bready,
output logic s_reg_axil_bvalid,
output logic [1:0] s_reg_axil_bresp,
output logic s_reg_axil_arready,
input wire s_reg_axil_arvalid,
input wire [8:0] s_reg_axil_araddr,
input wire [2:0] s_reg_axil_arprot,
input wire s_reg_axil_rready,
output logic s_reg_axil_rvalid,
output logic [31:0] s_reg_axil_rdata,
output logic [1:0] s_reg_axil_rresp
output logic s_reg_axil_awready,
input wire s_reg_axil_awvalid,
input wire [8:0] s_reg_axil_awaddr,
input wire [2:0] s_reg_axil_awprot,
output logic s_reg_axil_wready,
input wire s_reg_axil_wvalid,
input wire [31:0] s_reg_axil_wdata,
input wire [3:0] s_reg_axil_wstrb,
input wire s_reg_axil_bready,
output logic s_reg_axil_bvalid,
output logic [1:0] s_reg_axil_bresp,
output logic s_reg_axil_arready,
input wire s_reg_axil_arvalid,
input wire [8:0] s_reg_axil_araddr,
input wire [2:0] s_reg_axil_arprot,
input wire s_reg_axil_rready,
output logic s_reg_axil_rvalid,
output logic [31:0] s_reg_axil_rdata,
output logic [1:0] s_reg_axil_rresp,
// axil for m2s/s2m dma (can be combined into 1 or separate)
// axil for ring buffer managers
//MII Interface
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
// MDIO Interface
input i_Mdi,
output o_Mdo,
output o_MdoEn,
output o_Mdc,
output phy_rstn
);
tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in;
tcp_top_regfile_pkg::tcp_top_regfile__out_t tcp_hwif_out;
`define PROTO_ICMP 8'h1
`define PROTO_TCP 8'h6
`define PROTO_UDP 8'h11
localparam MAC_DATA_WIDTH = 8;
localparam AXIS_DATA_WIDTH = 8;
localparam AXIS_KEEP_WIDTH = ((AXIS_DATA_WIDTH+7)/8);
logic [AXIS_DATA_WIDTH-1:0] mac_tx_axis_tdata;
logic mac_tx_axis_tvalid;
logic mac_tx_axis_tready;
logic mac_tx_axis_tlast;
logic mac_tx_axis_tuser;
logic [AXIS_KEEP_WIDTH-1:0] mac_tx_axis_tkeep;
logic [AXIS_DATA_WIDTH-1:0] mac_rx_axis_tdata;
logic mac_rx_axis_tvalid;
logic mac_rx_axis_tready;
logic mac_rx_axis_tlast;
logic mac_rx_axis_tuser;
logic [AXIS_KEEP_WIDTH-1:0] mac_rx_axis_tkeep;
logic mac_tx_eth_hdr_valid;
logic mac_tx_eth_hdr_ready;
logic [47:0] mac_tx_eth_dest_mac;
logic [47:0] mac_tx_eth_src_mac;
logic [15:0] mac_tx_eth_type;
logic [AXIS_DATA_WIDTH-1:0] mac_tx_eth_payload_axis_tdata;
logic [AXIS_KEEP_WIDTH-1:0] mac_tx_eth_payload_axis_tkeep;
logic mac_tx_eth_payload_axis_tvalid;
logic mac_tx_eth_payload_axis_tready;
logic mac_tx_eth_payload_axis_tlast;
logic mac_tx_eth_payload_axis_tuser;
logic mac_rx_eth_hdr_valid;
logic mac_rx_eth_hdr_ready;
logic [47:0] mac_rx_eth_dest_mac;
logic [47:0] mac_rx_eth_src_mac;
logic [15:0] mac_rx_eth_type;
logic [AXIS_DATA_WIDTH-1:0] mac_rx_eth_payload_axis_tdata;
logic [AXIS_KEEP_WIDTH-1:0] mac_rx_eth_payload_axis_tkeep;
logic mac_rx_eth_payload_axis_tvalid;
logic mac_rx_eth_payload_axis_tready;
logic mac_rx_eth_payload_axis_tlast;
logic mac_rx_eth_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic tx_ip_hdr_valid;
logic tx_ip_hdr_ready;
logic [5:0] tx_ip_dscp;
logic [1:0] tx_ip_ecn;
logic [15:0] tx_ip_length;
logic [7:0] tx_ip_ttl;
logic [7:0] tx_ip_protocol;
logic [31:0] tx_ip_source_ip;
logic [31:0] tx_ip_dest_ip;
logic [7:0] tx_ip_payload_axis_tdata;
logic tx_ip_payload_axis_tvalid;
logic tx_ip_payload_axis_tready;
logic tx_ip_payload_axis_tlast;
logic tx_ip_payload_axis_tuser;
logic tcp_rx_ip_hdr_valid;
logic tcp_rx_ip_hdr_ready;
logic [47:0] tcp_rx_ip_eth_dest_mac;
logic [47:0] tcp_rx_ip_eth_src_mac;
logic [15:0] tcp_rx_ip_eth_type;
logic [3:0] tcp_rx_ip_version;
logic [3:0] tcp_rx_ip_ihl;
logic [5:0] tcp_rx_ip_dscp;
logic [1:0] tcp_rx_ip_ecn;
logic [15:0] tcp_rx_ip_length;
logic [15:0] tcp_rx_ip_identification;
logic [2:0] tcp_rx_ip_flags;
logic [12:0] tcp_rx_ip_fragment_offset;
logic [7:0] tcp_rx_ip_ttl;
logic [7:0] tcp_rx_ip_protocol;
logic [15:0] tcp_rx_ip_header_checksum;
logic [31:0] tcp_rx_ip_source_ip;
logic [31:0] tcp_rx_ip_dest_ip;
logic [7:0] tcp_rx_ip_payload_axis_tdata;
logic tcp_rx_ip_payload_axis_tvalid;
logic tcp_rx_ip_payload_axis_tready;
logic tcp_rx_ip_payload_axis_tlast;
logic tcp_rx_ip_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic tcp_tx_ip_hdr_valid;
logic tcp_tx_ip_hdr_ready;
logic [5:0] tcp_tx_ip_dscp;
logic [1:0] tcp_tx_ip_ecn;
logic [15:0] tcp_tx_ip_length;
logic [7:0] tcp_tx_ip_ttl;
logic [7:0] tcp_tx_ip_protocol;
logic [31:0] tcp_tx_ip_source_ip;
logic [31:0] tcp_tx_ip_dest_ip;
logic [7:0] tcp_tx_ip_payload_axis_tdata;
logic tcp_tx_ip_payload_axis_tvalid;
logic tcp_tx_ip_payload_axis_tready;
logic tcp_tx_ip_payload_axis_tlast;
logic tcp_tx_ip_payload_axis_tuser;
logic udp_ip_hdr_valid;
logic udp_ip_hdr_ready;
logic [47:0] udp_ip_eth_dest_mac;
logic [47:0] udp_ip_eth_src_mac;
logic [15:0] udp_ip_eth_type;
logic [3:0] udp_ip_version;
logic [3:0] udp_ip_ihl;
logic [5:0] udp_ip_dscp;
logic [1:0] udp_ip_ecn;
logic [15:0] udp_ip_length;
logic [15:0] udp_ip_identification;
logic [2:0] udp_ip_flags;
logic [12:0] udp_ip_fragment_offset;
logic [7:0] udp_ip_ttl;
logic [7:0] udp_ip_protocol;
logic [15:0] udp_ip_header_checksum;
logic [31:0] udp_ip_source_ip;
logic [31:0] udp_ip_dest_ip;
logic [7:0] udp_ip_payload_axis_tdata;
logic udp_ip_payload_axis_tvalid;
logic udp_ip_payload_axis_tready;
logic udp_ip_payload_axis_tlast;
logic udp_ip_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic udp_tx_ip_hdr_valid;
logic udp_tx_ip_hdr_ready;
logic [5:0] udp_tx_ip_dscp;
logic [1:0] udp_tx_ip_ecn;
logic [15:0] udp_tx_ip_length;
logic [7:0] udp_tx_ip_ttl;
logic [7:0] udp_tx_ip_protocol;
logic [31:0] udp_tx_ip_source_ip;
logic [31:0] udp_tx_ip_dest_ip;
logic [7:0] udp_tx_ip_payload_axis_tdata;
logic udp_tx_ip_payload_axis_tvalid;
logic udp_tx_ip_payload_axis_tready;
logic udp_tx_ip_payload_axis_tlast;
logic udp_tx_ip_payload_axis_tuser;
logic icmp_ip_hdr_valid;
logic icmp_ip_hdr_ready;
logic [47:0] icmp_ip_eth_dest_mac;
logic [47:0] icmp_ip_eth_src_mac;
logic [15:0] icmp_ip_eth_type;
logic [3:0] icmp_ip_version;
logic [3:0] icmp_ip_ihl;
logic [5:0] icmp_ip_dscp;
logic [1:0] icmp_ip_ecn;
logic [15:0] icmp_ip_length;
logic [15:0] icmp_ip_identification;
logic [2:0] icmp_ip_flags;
logic [12:0] icmp_ip_fragment_offset;
logic [7:0] icmp_ip_ttl;
logic [7:0] icmp_ip_protocol;
logic [15:0] icmp_ip_header_checksum;
logic [31:0] icmp_ip_source_ip;
logic [31:0] icmp_ip_dest_ip;
logic [7:0] icmp_ip_payload_axis_tdata;
logic icmp_ip_payload_axis_tvalid;
logic icmp_ip_payload_axis_tready;
logic icmp_ip_payload_axis_tlast;
logic icmp_ip_payload_axis_tuser;
// tx is less because IP adds it automatically.
logic icmp_tx_ip_hdr_valid;
logic icmp_tx_ip_hdr_ready;
logic [5:0] icmp_tx_ip_dscp;
logic [1:0] icmp_tx_ip_ecn;
logic [15:0] icmp_tx_ip_length;
logic [7:0] icmp_tx_ip_ttl;
logic [7:0] icmp_tx_ip_protocol;
logic [31:0] icmp_tx_ip_source_ip;
logic [31:0] icmp_tx_ip_dest_ip;
logic [7:0] icmp_tx_ip_payload_axis_tdata;
logic icmp_tx_ip_payload_axis_tvalid;
logic icmp_tx_ip_payload_axis_tready;
logic icmp_tx_ip_payload_axis_tlast;
logic icmp_tx_ip_payload_axis_tuser;
ntw_top_regfile_pkg::ntw_top_regfile__in_t hwif_in;
ntw_top_regfile_pkg::ntw_top_regfile__out_t hwif_out;
ntw_top_regfile u_ntw_top_regfile (
.clk (i_clk),
.rst (i_rst),
.s_axil_awready (s_reg_axil_awready),
.s_axil_awvalid (s_reg_axil_awvalid),
.s_axil_awaddr (s_reg_axil_awaddr),
.s_axil_awprot (s_reg_axil_awprot),
.s_axil_wready (s_reg_axil_wready),
.s_axil_wvalid (s_reg_axil_wvalid),
.s_axil_wdata (s_reg_axil_wdata),
.s_axil_wstrb (s_reg_axil_wstrb),
.s_axil_bready (s_reg_axil_bready),
.s_axil_bvalid (s_reg_axil_bvalid),
.s_axil_bresp (s_reg_axil_bresp),
.s_axil_arready (s_reg_axil_arready),
.s_axil_arvalid (s_reg_axil_arvalid),
.s_axil_araddr (s_reg_axil_araddr),
.s_axil_arprot (s_reg_axil_arprot),
.s_axil_rready (s_reg_axil_rready),
.s_axil_rvalid (s_reg_axil_rvalid),
.s_axil_rdata (s_reg_axil_rdata),
.s_axil_rresp (s_reg_axil_rresp),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
);
// eth wrapper
eth_wrapper #(
.MAC_DATA_WIDTH(MAC_DATA_WIDTH)
) u_eth_wrapper (
.rst (i_rst),
.clk_sys (i_clk),
// MII
.mii_rx_clk (mii_rx_clk),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_tx_clk (mii_tx_clk),
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.tx_axis_tdata (mac_tx_axis_tdata),
.tx_axis_tvalid (mac_tx_axis_tvalid),
.tx_axis_tready (mac_tx_axis_tready),
.tx_axis_tlast (mac_tx_axis_tlast),
.tx_axis_tuser (mac_tx_axis_tuser),
.tx_axis_tkeep (mac_tx_axis_tkeep),
.rx_axis_tdata (mac_rx_axis_tdata),
.rx_axis_tvalid (mac_rx_axis_tvalid),
.rx_axis_tready (mac_rx_axis_tready),
.rx_axis_tlast (mac_rx_axis_tlast),
.rx_axis_tuser (mac_rx_axis_tuser),
.rx_axis_tkeep (mac_rx_axis_tkeep),
.Mdi (i_Mdi),
.Mdo (o_Mdo),
.MdoEn (o_MdoEn),
.Mdc (o_Mdc)
);
eth_axis_rx #(
.DATA_WIDTH(MAC_DATA_WIDTH)
) u_mac_eth_axis_rx (
.clk (i_clk),
.rst (i_rst),
.s_axis_tdata (mac_rx_axis_tdata),
.s_axis_tvalid (mac_rx_axis_tvalid),
.s_axis_tready (mac_rx_axis_tready),
.s_axis_tlast (mac_rx_axis_tlast),
.s_axis_tuser (mac_rx_axis_tuser),
.s_axis_tkeep (mac_rx_axis_tkeep),
.m_eth_hdr_valid (mac_rx_eth_hdr_valid),
.m_eth_hdr_ready (mac_rx_eth_hdr_ready),
.m_eth_dest_mac (mac_rx_eth_dest_mac),
.m_eth_src_mac (mac_rx_eth_src_mac),
.m_eth_type (mac_rx_eth_type),
.m_eth_payload_axis_tdata (mac_rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep (mac_rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid (mac_rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready (mac_rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast (mac_rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser (mac_rx_eth_payload_axis_tuser),
.busy (),
.error_header_early_termination () // We can add this to a register
);
eth_axis_tx #(
.DATA_WIDTH(MAC_DATA_WIDTH)
) u_mac_eth_axis_tx (
.clk (i_clk),
.rst (i_rst),
.s_eth_hdr_valid (mac_tx_eth_hdr_valid),
.s_eth_hdr_ready (mac_tx_eth_hdr_ready),
.s_eth_dest_mac (mac_tx_eth_dest_mac),
.s_eth_src_mac (mac_tx_eth_src_mac),
.s_eth_type (mac_tx_eth_type),
.s_eth_payload_axis_tdata (mac_tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep (mac_tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid (mac_tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready (mac_tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast (mac_tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser (mac_tx_eth_payload_axis_tuser),
.m_axis_tdata (mac_tx_axis_tdata),
.m_axis_tvalid (mac_tx_axis_tvalid),
.m_axis_tready (mac_tx_axis_tready),
.m_axis_tlast (mac_tx_axis_tlast),
.m_axis_tuser (mac_tx_axis_tuser),
.m_axis_tkeep (mac_tx_axis_tkeep),
.busy ()
);
// this is 8 bit only, we should assert that data width is 8 at this point.
ip_complete #(
.ARP_CACHE_ADDR_WIDTH(7), // memory usage is 81 bits per entry
.ARP_REQUEST_RETRY_COUNT(4),
.ARP_REQUEST_RETRY_INTERVAL(125000000*2), // these are defaults
.ARP_REQUEST_TIMEOUT(125000000*30)
) u_ip_complete (
.clk (i_clk),
.rst (i_rst),
.s_eth_hdr_valid (mac_rx_eth_hdr_valid),
.s_eth_hdr_ready (mac_rx_eth_hdr_ready),
.s_eth_dest_mac (mac_rx_eth_dest_mac),
.s_eth_src_mac (mac_rx_eth_src_mac),
.s_eth_type (mac_rx_eth_type),
.s_eth_payload_axis_tdata (mac_rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid (mac_rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready (mac_rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast (mac_rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser (mac_rx_eth_payload_axis_tuser),
.m_eth_hdr_valid (mac_tx_eth_hdr_valid),
.m_eth_hdr_ready (mac_tx_eth_hdr_ready),
.m_eth_dest_mac (mac_tx_eth_dest_mac),
.m_eth_src_mac (mac_tx_eth_src_mac),
.m_eth_type (mac_tx_eth_type),
.m_eth_payload_axis_tdata (mac_tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid (mac_tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready (mac_tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast (mac_tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser (mac_tx_eth_payload_axis_tuser),
.s_ip_hdr_valid (tx_ip_hdr_valid),
.s_ip_hdr_ready (tx_ip_hdr_ready),
.s_ip_dscp (tx_ip_dscp),
.s_ip_ecn (tx_ip_ecn),
.s_ip_length (tx_ip_length),
.s_ip_ttl (tx_ip_ttl),
.s_ip_protocol (tx_ip_protocol),
.s_ip_source_ip (tx_ip_source_ip),
.s_ip_dest_ip (tx_ip_dest_ip),
.s_ip_payload_axis_tdata (tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid (tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready (tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast (tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser (tx_ip_payload_axis_tuser),
.m_ip_hdr_valid (rx_ip_hdr_valid),
.m_ip_hdr_ready (rx_ip_hdr_ready),
.m_ip_eth_dest_mac (rx_ip_eth_dest_mac),
.m_ip_eth_src_mac (rx_ip_eth_src_mac),
.m_ip_eth_type (rx_ip_eth_type),
.m_ip_version (rx_ip_version),
.m_ip_ihl (rx_ip_ihl),
.m_ip_dscp (rx_ip_dscp),
.m_ip_ecn (rx_ip_ecn),
.m_ip_length (rx_ip_length),
.m_ip_identification (rx_ip_identification),
.m_ip_flags (rx_ip_flags),
.m_ip_fragment_offset (rx_ip_fragment_offset),
.m_ip_ttl (rx_ip_ttl),
.m_ip_protocol (rx_ip_protocol),
.m_ip_header_checksum (rx_ip_header_checksum),
.m_ip_source_ip (rx_ip_source_ip),
.m_ip_dest_ip (rx_ip_dest_ip),
.m_ip_payload_axis_tdata (rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid (rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready (rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast (rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser (rx_ip_payload_axis_tuser),
.rx_busy (), // should go to stats register
.tx_busy (), // should go to stats register
.rx_error_header_early_termination (), // should go to stats register
.rx_error_payload_early_termination (), // should go to stats register
.rx_error_invalid_header (), // should go to stats register
.rx_error_invalid_checksum (), // should go to stats register
.tx_error_payload_early_termination (), // should go to stats register
.tx_error_arp_failed (), // should go to stats register
.local_mac (48'h020000aabbcc), // should be a register
.local_ip (32'hac000002), // should be a register
.gateway_ip (32'hac000001), // should be a register
.subnet_mask (32'hffffff00), // should be a register
.clear_arp_cache ('0) // should come from sw
);
ip_demux #(
.M_COUNT(3),
.DATA_WIDTH(MAC_DATA_WIDTH)
) u_ip_demux (
.clk (i_clk),
.rst (i_rst),
.s_ip_hdr_valid (rx_ip_hdr_valid),
.s_ip_hdr_ready (rx_ip_hdr_ready),
.s_eth_dest_mac (rx_ip_eth_dest_mac),
.s_eth_src_mac (rx_ip_eth_src_mac),
.s_eth_type (rx_ip_eth_type),
.s_ip_version (rx_ip_version),
.s_ip_ihl (rx_ip_ihl),
.s_ip_dscp (rx_ip_dscp),
.s_ip_ecn (rx_ip_ecn),
.s_ip_length (rx_ip_length),
.s_ip_identification (rx_ip_identification),
.s_ip_flags (rx_ip_flags),
.s_ip_fragment_offset (rx_ip_fragment_offset),
.s_ip_ttl (rx_ip_ttl),
.s_ip_protocol (rx_ip_protocol),
.s_ip_header_checksum (rx_ip_header_checksum),
.s_ip_source_ip (rx_ip_source_ip),
.s_ip_dest_ip (rx_ip_dest_ip),
.s_ip_payload_axis_tdata (rx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid (rx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready (rx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast (rx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser (rx_ip_payload_axis_tuser),
.m_ip_hdr_valid ({icmp_ip_hdr_valid, udp_ip_hdr_valid, tcp_tx_ip_hdr_valid}),
.m_ip_hdr_ready ({icmp_ip_hdr_ready, udp_ip_hdr_ready, tcp_tx_ip_hdr_ready}),
.m_eth_dest_mac ({icmp_ip_eth_dest_mac, udp_ip_eth_dest_mac, tcp_tx_ip_eth_dest_mac}),
.m_eth_src_mac ({icmp_ip_eth_src_mac, udp_ip_eth_src_mac, tcp_tx_ip_eth_src_mac}),
.m_eth_type ({icmp_ip_eth_type, udp_ip_eth_type, tcp_tx_ip_eth_type}),
.m_ip_version ({icmp_ip_version, udp_ip_version, tcp_tx_ip_version}),
.m_ip_ihl ({icmp_ip_ihl, udp_ip_ihl, tcp_tx_ip_ihl}),
.m_ip_dscp ({icmp_ip_dscp, udp_ip_dscp, tcp_tx_ip_dscp}),
.m_ip_ecn ({icmp_ip_ecn, udp_ip_ecn, tcp_tx_ip_ecn}),
.m_ip_length ({icmp_ip_length, udp_ip_length, tcp_tx_ip_length}),
.m_ip_identification ({icmp_ip_identification, udp_ip_identification, tcp_tx_ip_identification}),
.m_ip_flags ({icmp_ip_flags, udp_ip_flags, tcp_tx_ip_flags}),
.m_ip_fragment_offset ({icmp_ip_fragment_offset, udp_ip_fragment_offset, tcp_tx_ip_fragment_offset}),
.m_ip_ttl ({icmp_ip_ttl, udp_ip_ttl, tcp_tx_ip_ttl}),
.m_ip_protocol ({icmp_ip_protocol, udp_ip_protocol, tcp_tx_ip_protocol}),
.m_ip_header_checksum ({icmp_ip_header_checksum, udp_ip_header_checksum, tcp_tx_ip_header_checksum}),
.m_ip_source_ip ({icmp_ip_source_ip, udp_ip_source_ip, tcp_tx_ip_source_ip}),
.m_ip_dest_ip ({icmp_ip_dest_ip, udp_ip_dest_ip, tcp_tx_ip_dest_ip}),
.m_ip_payload_axis_tdata ({icmp_ip_payload_axis_tdata, udp_ip_payload_axis_tdata, tcp_tx_ip_payload_axis_tdata}),
.m_ip_payload_axis_tkeep (),
.m_ip_payload_axis_tvalid ({icmp_ip_payload_axis_tvalid, udp_ip_payload_axis_tvalid, tcp_tx_ip_payload_axis_tvalid}),
.m_ip_payload_axis_tready ({icmp_ip_payload_axis_tready, udp_ip_payload_axis_tready, tcp_tx_ip_payload_axis_tready}),
.m_ip_payload_axis_tlast ({icmp_ip_payload_axis_tlast, udp_ip_payload_axis_tlast, tcp_tx_ip_payload_axis_tlast}),
.m_ip_payload_axis_tid (),
.m_ip_payload_axis_tdest (),
.m_ip_payload_axis_tuser ({icmp_ip_payload_axis_tuser, udp_ip_payload_axis_tuser, tcp_tx_ip_payload_axis_tuser}),
.enable ('1),
.drop (ip_demux_drop),
.select (ip_demux_sel)
);
tcp #(
.NUM_TCP(NUM_TCP)
) tcp (
.i_clk (i_clk),
.i_rst (i_rst),
.i_clk (i_clk),
.i_rst (i_rst),
.s_reg_axil_awready (s_reg_axil_awready),
.s_reg_axil_awvalid (s_reg_axil_awvalid),
.s_reg_axil_awaddr (s_reg_axil_awaddr),
.s_reg_axil_awprot (s_reg_axil_awprot),
.s_reg_axil_wready (s_reg_axil_wready),
.s_reg_axil_wvalid (s_reg_axil_wvalid),
.s_reg_axil_wdata (s_reg_axil_wdata),
.s_reg_axil_wstrb (s_reg_axil_wstrb),
.s_reg_axil_bready (s_reg_axil_bready),
.s_reg_axil_bvalid (s_reg_axil_bvalid),
.s_reg_axil_bresp (s_reg_axil_bresp),
.s_reg_axil_arready (s_reg_axil_arready),
.s_reg_axil_arvalid (s_reg_axil_arvalid),
.s_reg_axil_araddr (s_reg_axil_araddr),
.s_reg_axil_arprot (s_reg_axil_arprot),
.s_reg_axil_rready (s_reg_axil_rready),
.s_reg_axil_rvalid (s_reg_axil_rvalid),
.s_reg_axil_rdata (s_reg_axil_rdata),
.s_reg_axil_rresp (s_reg_axil_rresp)
.s_cpuif_req (hwif_out.tcp_top.req),
.s_cpuif_req_is_wr (hwif_out.tcp_top.req_is_wr),
.s_cpuif_addr (hwif_out.tcp_top.addr),
.s_cpuif_wr_data (hwif_out.tcp_top.wr_data),
.s_cpuif_wr_biten (hwif_out.tcp_top.wr_biten),
.s_cpuif_req_stall_wr (),
.s_cpuif_req_stall_rd (),
.s_cpuif_rd_ack (hwif_in.tcp_top.rd_ack),
.s_cpuif_rd_err (),
.s_cpuif_rd_data (hwif_in.tcp_top.rd_data),
.s_cpuif_wr_ack (hwif_in.tcp_top.wr_ack),
.s_cpuif_wr_err ()
);
endmodule

244
hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
View File

@@ -5,25 +5,63 @@ module tcp #(
input i_clk,
input i_rst,
output logic s_reg_axil_awready,
input wire s_reg_axil_awvalid,
input wire [8:0] s_reg_axil_awaddr,
input wire [2:0] s_reg_axil_awprot,
output logic s_reg_axil_wready,
input wire s_reg_axil_wvalid,
input wire [31:0] s_reg_axil_wdata,
input wire [3:0] s_reg_axil_wstrb,
input wire s_reg_axil_bready,
output logic s_reg_axil_bvalid,
output logic [1:0] s_reg_axil_bresp,
output logic s_reg_axil_arready,
input wire s_reg_axil_arvalid,
input wire [8:0] s_reg_axil_araddr,
input wire [2:0] s_reg_axil_arprot,
input wire s_reg_axil_rready,
output logic s_reg_axil_rvalid,
output logic [31:0] s_reg_axil_rdata,
output logic [1:0] s_reg_axil_rresp
input wire m_cpuif_req,
input wire m_cpuif_req_is_wr,
input wire [4:0] m_cpuif_addr,
input wire [31:0] m_cpuif_wr_data,
input wire [31:0] m_cpuif_wr_biten,
output wire m_cpuif_req_stall_wr,
output wire m_cpuif_req_stall_rd,
output wire m_cpuif_rd_ack,
output wire m_cpuif_rd_err,
output wire [31:0] m_cpuif_rd_data,
output wire m_cpuif_wr_ack,
output wire m_cpuif_wr_err
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_ip_eth_dest_mac,
input wire [47:0] s_ip_eth_src_mac,
input wire [15:0] s_ip_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid
output wire s_ip_payload_axis_tready
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid
input wire m_ip_payload_axis_tready
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser
);
tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in;
@@ -34,25 +72,18 @@ tcp_top_regfile u_tcp_top_regfile (
.clk (i_clk),
.rst (i_rst),
.s_axil_awready (s_reg_axil_awready),
.s_axil_awvalid (s_reg_axil_awvalid),
.s_axil_awaddr (s_reg_axil_awaddr),
.s_axil_awprot (s_reg_axil_awprot),
.s_axil_wready (s_reg_axil_wready),
.s_axil_wvalid (s_reg_axil_wvalid),
.s_axil_wdata (s_reg_axil_wdata),
.s_axil_wstrb (s_reg_axil_wstrb),
.s_axil_bready (s_reg_axil_bready),
.s_axil_bvalid (s_reg_axil_bvalid),
.s_axil_bresp (s_reg_axil_bresp),
.s_axil_arready (s_reg_axil_arready),
.s_axil_arvalid (s_reg_axil_arvalid),
.s_axil_araddr (s_reg_axil_araddr),
.s_axil_arprot (s_reg_axil_arprot),
.s_axil_rready (s_reg_axil_rready),
.s_axil_rvalid (s_reg_axil_rvalid),
.s_axil_rdata (s_reg_axil_rdata),
.s_axil_rresp (s_reg_axil_rresp),
.s_cpuif_req (s_cpuif_req),
.s_cpuif_req_is_wr (s_cpuif_req_is_wr),
.s_cpuif_addr (s_cpuif_addr),
.s_cpuif_wr_data (s_cpuif_wr_data),
.s_cpuif_wr_biten (s_cpuif_wr_biten),
.s_cpuif_req_stall_wr (),
.s_cpuif_req_stall_rd (),
.s_cpuif_rd_ack (s_cpuif_rd_ack),
.s_cpuif_rd_err (),
.s_cpuif_rd_data (s_cpuif_rd_data),
.s_cpuif_wr_ack (s_cpuif_wr_ack),
.s_cpuif_wr_err (),
.hwif_in (tcp_hwif_in),
.hwif_out (tcp_hwif_out)
@@ -70,22 +101,6 @@ logic m2s_tx_axis_tlast;
logic [DEST_WIDTH-1:0] m2s_tx_axis_tdest;
logic [USER_WIDTH-1:0] m2s_tx_axis_tuser;
logic [NUM_TCP*DATA_WIDTH-1:0] tcp_tx_axis_tdata;
logic [NUM_TCP*KEEP_WIDTH-1:0] tcp_tx_axis_tkeep;
logic [NUM_TCP-1:0] tcp_tx_axis_tvalid;
logic [NUM_TCP-1:0] tcp_tx_axis_tready;
logic [NUM_TCP-1:0] tcp_tx_axis_tlast;
logic [NUM_TCP*DEST_WIDTH-1:0] tcp_tx_axis_tdest;
logic [NUM_TCP*USER_WIDTH-1:0] tcp_tx_axis_tuser;
logic [NUM_TCP*DATA_WIDTH-1:0] tcp_rx_axis_tdata;
logic [NUM_TCP*KEEP_WIDTH-1:0] tcp_rx_axis_tkeep;
logic [NUM_TCP-1:0] tcp_rx_axis_tvalid;
logic [NUM_TCP-1:0] tcp_rx_axis_tready;
logic [NUM_TCP-1:0] tcp_rx_axis_tlast;
logic [NUM_TCP*DEST_WIDTH-1:0] tcp_rx_axis_tdest;
logic [NUM_TCP*USER_WIDTH-1:0] tcp_rx_axis_tuser;
logic [DATA_WIDTH-1:0] s2m_rx_axis_tdata;
logic [KEEP_WIDTH-1:0] s2m_rx_axis_tkeep;
logic s2m_rx_axis_tvalid;
@@ -94,73 +109,56 @@ logic s2m_rx_axis_tlast;
logic [DEST_WIDTH-1:0] s2m_rx_axis_tdest;
logic [USER_WIDTH-1:0] s2m_rx_axis_tuser;
logic [NUM_TCP-1:0] tcp_rx_ip_hdr_valid;
logic [NUM_TCP-1:0] tcp_rx_ip_hdr_ready;
logic [NUM_TCP*48-1:0] tcp_rx_eth_dest_mac;
logic [NUM_TCP*48-1:0] tcp_rx_eth_src_mac;
logic [NUM_TCP*16-1:0] tcp_rx_eth_type;
logic [NUM_TCP*4-1:0] tcp_rx_ip_version;
logic [NUM_TCP*4-1:0] tcp_rx_ip_ihl;
logic [NUM_TCP*6-1:0] tcp_rx_ip_dscp;
logic [NUM_TCP*2-1:0] tcp_rx_ip_ecn;
logic [NUM_TCP*16-1:0] tcp_rx_ip_length;
logic [NUM_TCP*16-1:0] tcp_rx_ip_identification;
logic [NUM_TCP*3-1:0] tcp_rx_ip_flags;
logic [NUM_TCP*13-1:0] tcp_rx_ip_fragment_offset;
logic [NUM_TCP*8-1:0] tcp_rx_ip_ttl;
logic [NUM_TCP*8-1:0] tcp_rx_ip_protocol;
logic [NUM_TCP*16-1:0] tcp_rx_ip_header_checksum;
logic [NUM_TCP*32-1:0] tcp_rx_ip_source_ip;
logic [NUM_TCP*32-1:0] tcp_rx_ip_dest_ip;
logic [NUM_TCP*DATA_WIDTH-1:0] tcp_rx_ip_payload_axis_tdata;
logic [NUM_TCP*KEEP_WIDTH-1:0] tcp_rx_ip_payload_axis_tkeep;
logic [NUM_TCP-1:0] tcp_rx_ip_payload_axis_tvalid;
logic [NUM_TCP-1:0] tcp_rx_ip_payload_axis_tready;
logic [NUM_TCP-1:0] tcp_rx_ip_payload_axis_tlast;
logic [NUM_TCP*ID_WIDTH-1:0] tcp_rx_ip_payload_axis_tid;
logic [NUM_TCP*DEST_WIDTH-1:0] tcp_rx_ip_payload_axis_tdest;
logic [NUM_TCP*USER_WIDTH-1:0] tcp_rx_ip_payload_axis_tuser;
logic [NUM_TCP-1:0] tcp_tx_ip_hdr_valid;
logic [NUM_TCP-1:0] tcp_tx_ip_hdr_ready;
logic [NUM_TCP*6-1:0] tcp_tx_ip_dscp;
logic [NUM_TCP*2-1:0] tcp_tx_ip_ecn;
logic [NUM_TCP*16-1:0] tcp_tx_ip_length;
logic [NUM_TCP*8-1:0] tcp_tx_ip_ttl;
logic [NUM_TCP*8-1:0] tcp_tx_ip_protocol;
logic [NUM_TCP*32-1:0] tcp_tx_ip_source_ip;
logic [NUM_TCP*32-1:0] tcp_tx_ip_dest_ip;
logic [NUM_TCP*DATA_WIDTH-1:0] tcp_tx_ip_payload_axis_tdata;
logic [NUM_TCP-1:0] tcp_tx_ip_payload_axis_tvalid;
logic [NUM_TCP-1:0] tcp_tx_ip_payload_axis_tready;
logic [NUM_TCP-1:0] tcp_tx_ip_payload_axis_tlast;
logic [NUM_TCP*USER_WIDTH-1:0] tcp_tx_ip_payload_axis_tuser;
//m2s dma
//s2m dma
// tx_stream demux
axis_demux #(
.M_COUNT(NUM_TCP),
.DATA_WIDTH(DATA_WIDTH),
.M_DEST_WIDTH(DEST_WIDTH),
.DEST_ENABLE(1),
.TDEST_ROUTE(1)
) tx_stream_demux (
.clk (i_clk),
.rst (i_rst),
// tx_stream demux (ip)
.s_axis_tdata (m2s_tx_axis_tdata),
.s_axis_tkeep (m2s_tx_axis_tkeep),
.s_axis_tvalid (m2s_tx_axis_tvalid),
.s_axis_tready (m2s_tx_axis_tready),
.s_axis_tlast (m2s_tx_axis_tlast),
.s_axis_tid ('0),
.s_axis_tdest (m2s_tx_axis_tdest),
.s_axis_tuser (m2s_tx_axis_tuser),
.m_axis_tdata (tcp_tx_axis_tdata),
.m_axis_tkeep (tcp_tx_axis_tkeep),
.m_axis_tvalid (tcp_tx_axis_tvalid),
.m_axis_tready (tcp_tx_axis_tready),
.m_axis_tlast (tcp_tx_axis_tlast),
.m_axis_tid (),
.m_axis_tdest (tcp_tx_axis_tdest),
.m_axis_tuser (tcp_tx_axis_tuser),
.enable ('1),
.drop ('0),
.select ('0)
);
// rx_stream arb
axis_arb_mux #(
.S_COUNT(NUM_TCP),
.DATA_WIDTH(DATA_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(8)
) rx_stream_demux (
.clk (i_clk),
.rst (i_rst),
.s_axis_tdata (tcp_rx_axis_tdata),
.s_axis_tkeep (tcp_rx_axis_tkeep),
.s_axis_tvalid (tcp_rx_axis_tvalid),
.s_axis_tready (tcp_rx_axis_tready),
.s_axis_tlast (tcp_rx_axis_tlast),
.s_axis_tid ('0),
.s_axis_tdest (tcp_rx_axis_tdest),
.s_axis_tuser (tcp_rx_axis_tuser),
.m_axis_tdata (s2m_rx_axis_tdata),
.m_axis_tkeep (s2m_rx_axis_tkeep),
.m_axis_tvalid (s2m_rx_axis_tvalid),
.m_axis_tready (s2m_rx_axis_tready),
.m_axis_tlast (s2m_rx_axis_tlast),
.m_axis_tid (),
.m_axis_tdest (s2m_rx_axis_tdest),
.m_axis_tuser (s2m_rx_axis_tuser)
);
// rx_stream arb (ip)
generate
@@ -195,22 +193,6 @@ generate
.s_cpuif_rd_data (tcp_hwif_in.tcp_streams[i].rd_data),
.s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack),
.s_cpuif_wr_err (),
.s_axis_tdata (tcp_tx_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH]),
.s_axis_tkeep (tcp_tx_axis_tkeep[i*KEEP_WIDTH+:KEEP_WIDTH]),
.s_axis_tvalid (tcp_tx_axis_tvalid[i]),
.s_axis_tready (tcp_tx_axis_tready[i]),
.s_axis_tlast (tcp_tx_axis_tlast[i]),
.s_axis_tdest (tcp_tx_axis_tdest[i*DEST_WIDTH+:DEST_WIDTH]),
.s_axis_tuser (tcp_tx_axis_tuser[i*USER_WIDTH+:USER_WIDTH]),
.m_axis_tdata (tcp_rx_axis_tdata[i*DATA_WIDTH+:DATA_WIDTH]),
.m_axis_tkeep (tcp_rx_axis_tkeep[i*KEEP_WIDTH+:KEEP_WIDTH]),
.m_axis_tvalid (tcp_rx_axis_tvalid[i]),
.m_axis_tready (tcp_rx_axis_tready[i]),
.m_axis_tlast (tcp_rx_axis_tlast[i]),
.m_axis_tdest (tcp_rx_axis_tdest[i*DEST_WIDTH+:DEST_WIDTH]),
.m_axis_tuser (tcp_rx_axis_tuser[i*USER_WIDTH+:USER_WIDTH])
);
end
endgenerate

57
hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
View File

@@ -20,21 +20,50 @@ module tcp_stream #(
output wire s_cpuif_wr_ack,
output wire s_cpuif_wr_err,
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_ip_eth_dest_mac,
input wire [47:0] s_ip_eth_src_mac,
input wire [15:0] s_ip_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [7:0] s_ip_payload_axis_tdata,
input wire s_ip_payload_axis_tvalid
output wire s_ip_payload_axis_tready
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid
input wire m_ip_payload_axis_tready
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser
);
// regs