Update so I can switch computers

hw/super6502_fpga/src/sub/network_processor/sim/cocotb/Makefile

@@ -19,6 +19,6 @@ GPI_IMPL := vpi
 
 export PYTHONPATH := $(PWD)/tests:$(PYTHONPATH)
 export TOPLEVEL_LANG
-MODULE=sanity
+MODULE=tcp_test
 
 include $(shell cocotb-config --makefiles)/Makefile.sim

hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/tcp_test.py

@@ -39,18 +39,6 @@ async def test_simple(dut):
 
     await tb.cycle_reset()
 
-    test_data = bytearray([x % 256 for x in range(256)])
+    await tb.axil_master.write_dword(0x210, 0x3)
-
-    tb.axil_ram.write(0x1000, test_data)
-    tb.axil_ram.write(0x2000, test_data)
-
-    tb.axil_ram.write_dword(0x00000400, 0x00001000)
-    tb.axil_ram.write_dword(0x00000404, 64)
-    tb.axil_ram.write_dword(0x00000408, 0)
-    tb.axil_ram.write_dword(0x0000040c, 0x000000400)
-
-    await tb.axil_master.write_dword(0x22c, 0x000)
-    await tb.axil_master.write_dword(0x220, 0x400)
-    await tb.axil_master.write_dword(0x224, 0x400)
 
     await Timer(Decimal(CLK_PERIOD_NS * 400), units='ns')

hw/super6502_fpga/src/sub/network_processor/sources.list

@@ -7,6 +7,8 @@ src/regs/mac_regs.sv
 src/regs/ntw_top_regfile_pkg.sv
 src/regs/ntw_top_regfile.sv
 src/network_processor.sv
+src/tcp_pkg.sv
+src/tcp_tx_ctrl.sv
 src/tcp_state_manager.sv
 src/tcp_stream.sv
 src/tcp.sv

hw/super6502_fpga/src/sub/network_processor/src/tcp_packet_generator.sv

@@ -0,0 +1,18 @@
+module tcp_packet_generator (
+    input  wire             i_clk,
+    input  wire             i_rst
+
+    axis_intf.SLAVE         s_axis_data,
+
+    input  wire [31:0]      i_seq_number,
+    input  wire [31:0]      i_ack_number,
+    input  wire [15:0]      i_source_port,
+    input  wire [15:0]      i_dest_port,
+    input  wire [7:0]       i_flags,
+    input  wire [15:0]      i_window_size
+    input  wire             i_hdr_valid
+
+    ip_intf.MASTER          m_ip
+);
+
+endmodule

hw/super6502_fpga/src/sub/network_processor/src/tcp_pkg.sv

@@ -0,0 +1,18 @@
+package tcp_pkg;
+
+    typedef enum logic [2:0] {
+        TX_CTRL_NOP,
+        TX_CTRL_SEND_SYN,
+        TX_CTRL_SEND_ACK,
+        TX_CTRL_SEND_SYNACK,
+        TX_CTRL_SEND_FIN
+    } tx_ctrl_t;
+
+    typedef enum logic [2:0] {
+        RX_MSG_NOP,
+        RX_MSG_RECV_SYN,
+        RX_MSG_RECV_ACK,
+        RX_MSG_RECV_FIN,
+        RX_MSG_RECV_SYNACK
+    } rx_msg_t;
+endpackage

hw/super6502_fpga/src/sub/network_processor/src/tcp_state_manager.sv

@@ -0,0 +1,74 @@
+import tcp_pkg::*;
+
+module tcp_state_manager(
+    input  wire                 i_clk,
+    input  wire                 i_rst,
+
+    input  wire                 i_enable,
+
+    input  wire                 i_open,
+    output logic                o_open_clr,
+    input  wire                 i_close,
+    output logic                o_close_clr,
+
+    output tcp_pkg::tx_ctrl_t   o_tx_ctrl,
+    output logic                o_tx_ctrl_valid,
+    input  logic                i_tx_ctrl_ack,
+
+    input tcp_pkg::rx_msg_t     i_rx_msg,
+    input  wire                 i_rx_msg_valid,
+    output logic                o_rx_msg_ack
+);
+
+enum logic [3:0] {
+    IDLE,
+    SYN_RCVD,       // In this design, this state should not be reached!
+    SYN_SENT,
+    ESTABLISHED,
+    WAIT_CLOSE,
+    LAST_ACK,
+    TIME_WAIT,
+    FIN_WAIT_1,
+    FIN_WAIT_2
+} tcp_state, tcp_state_next;
+
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        tcp_state <= IDLE;
+    end else begin
+        if (i_enable) begin
+            tcp_state <= IDLE;
+        end else begin
+            tcp_state <= tcp_state_next;
+        end
+    end
+end
+
+always_comb begin
+    tcp_state_next = tcp_state;
+
+    o_tx_ctrl = TX_CTRL_NOP;
+    o_tx_ctrl_valid = '0;
+
+    o_rx_msg_ack = '0;
+
+    case (tcp_state)
+        IDLE: begin
+            if (i_open) begin
+                o_tx_ctrl = TX_CTRL_SEND_SYN;
+                o_tx_ctrl_valid = '1;
+
+                if (i_tx_ctrl_ack) begin
+                    tcp_state_next = SYN_SENT;
+                end
+            end
+        end
+
+        SYN_SENT: begin
+            $display("SYN_SENT not implemented");
+        end
+    endcase
+end
+
+endmodule

hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv

@@ -36,6 +36,19 @@ axis_intf m2s_post_saf_axis();
 tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in;
 tcp_stream_regs_pkg::tcp_stream_regs__out_t hwif_out;
 
+tcp_pkg::tx_ctrl_t tx_ctrl;
+logic tx_ctrl_valid;
+logic tx_ctrl_ack;
+
+logic [31:0]         o_seq_number;
+logic [31:0]         o_ack_number;
+logic [7:0]          o_flags;
+logic [15:0]         o_window_size;
+logic                o_hdr_vali;
+
+tcp_pkg::rx_msg_t rx_msg;
+
+
 
 tcp_stream_regs u_tcp_stream_regs (
     .clk                    (clk),
@@ -81,7 +94,26 @@ m2s_dma #(
     .m_axis                     (m2s_axis)
 );
 
-// SAF
+
+// tcp state manager
+tcp_state_manager u_tcp_state_manager (
+    .i_clk                      (clk),
+    .i_rst                      (rst),
+
+    .i_enable                   (hwif_out.control.enable.value),
+
+    .i_open                     (hwif_out.control.open.value),
+    .o_open_clr                 (hwif_in.control.open.hwclr),
+    .i_close                    (hwif_out.control.close.value),
+    .o_close_clr                (hwif_in.control.close.hwclr),
+
+    .o_tx_ctrl                  (tx_ctrl),
+    .o_tx_ctrl_valid            (tx_ctrl_valid),
+    .i_tx_ctrl_ack              (tx_ctrl_ack)
+);
+
+
+// tx buffer
 axis_fifo #(
     .DEPTH(4096),
     .DATA_WIDTH(DATA_WIDTH),
@@ -118,14 +150,39 @@ axis_fifo #(
     .status_good_frame          ()
 );
 
-
-// tcp state manager
-
-// tx buffer
-
 // tx control
+tcp_tx_ctrl u_tcp_tx_ctrl (
+    .i_clk                      (clk),
+    .i_rst                      (rst),
+
+    .i_tx_ctrl                  (tx_ctrl),
+    .i_tx_ctrl_valid            (tx_ctrl_valid),
+    .o_tx_ctrl_ack              (tx_ctrl_ack),
+
+    .o_seq_number               (w_tx_seq_number),
+    .o_ack_number               (w_tx_ack_number),
+    .o_flags                    (w_tx_flags),
+    .o_window_size              (w_tx_window_size),
+    .o_hdr_valid                (w_tx_hdr_valid)
+);
 
 // packet generator
+tcp_packet_generator u_tcp_packet_generator (
+    .i_clk                      (clk),
+    .i_rst                      (rst),
+
+    .s_axis_data                (m2s_post_saf_axis),
+
+    .i_seq_number               (w_tx_seq_number),
+    .i_ack_number               (w_tx_ack_number),
+    .i_source_port              (hwif_out.source_port.d.value),
+    .i_dest_port                (hwif_out.dest_port.d.value),
+    .i_flags                    (w_tx_flags),
+    .i_window_size              (w_tx_window_size),
+    .i_hdr_valid                (w_tx_hdr_valid)
+
+    .m_ip                       (m_ip_tx)
+);
 
 // parser
 

hw/super6502_fpga/src/sub/network_processor/src/tcp_tx_ctrl.sv

@@ -0,0 +1,38 @@
+import tcp_pkg::*;
+
+module tcp_tx_ctrl(
+    input i_clk,
+    input i_rst,
+
+    input  tcp_pkg::tx_ctrl_t   i_tx_ctrl,
+    input  logic                i_tx_ctrl_valid,
+    output logic                o_tx_ctrl_ack,
+
+    output logic [31:0]         o_seq_number,
+    output logic [31:0]         o_ack_number,
+    output logic [7:0]          o_flags,
+    output logic [15:0]         o_window_size,
+    output logic                o_hdr_valid
+);
+
+enum logic [2:0] {IDLE, SEND_SYN} state, state_next;
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        state <= IDLE;
+    end else begin
+        state <= state_next;
+    end
+end
+
+always_comb begin
+    case (state)
+        IDLE: begin
+            if (i_tx_ctrl) begin
+                o_tx_ctrl_ack = '1;
+            end
+        end
+    endcase
+end
+
+endmodule