diff --git a/Makefile b/Makefile
index 8c9523e..a56ae02 100644
--- a/Makefile
+++ b/Makefile
@@ -14,6 +14,9 @@ fpga_image: $(INIT_HEX)
 sim: $(INIT_HEX)
 	$(MAKE) -C hw/super6502_fpga/src/sim
 
+pgm:
+	$(MAKE) -C hw/super6502_fpga pgm
+
 waves: sim
 	gtkwave hw/super6502_fpga/src/sim/sim_top.vcd
 
diff --git a/hw/super6502_fpga/Makefile b/hw/super6502_fpga/Makefile
index d6fcf1b..bf0d84c 100644
--- a/hw/super6502_fpga/Makefile
+++ b/hw/super6502_fpga/Makefile
@@ -9,8 +9,11 @@ all: $(SUPER6502_FPGA_BITSTREAM)
 $(SUPER6502_FPGA_BITSTREAM): $(SUPER6502_FPGA_SOURCES) $(SUPER6502_FPGA_PROJECT)
 	efx_run.py $(SUPER6502_FPGA_PROJECT)
 
+pgm:
+	efx_run.py $(SUPER6502_FPGA_PROJECT) --flow program --pgm_opts mode=jtag
+
 .PHONY: clean
 clean:
 	rm -rf work_*
 	rm -rf outflow
-	rm -rf init_hex.mem
\ No newline at end of file
+	rm -rf init_hex.mem