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Throw everything up

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I think that previously, I had not actually commited any of this to git.
This adds all of the new effinix stuff that I had been working on for
months.

The gist of all of this is that the intel fpga is expensive and does not
exist, whereas the effinix ones are not as expensive and more existant.
This redoes the project to use the dev board, as well as a custom board
that I may or may not make.
This commit is contained in:
Byron Lathi
2022-10-04 17:15:49 -05:00
parent 5c72c574e5
commit fcae23785e
43 changed files with 10213 additions and 1 deletions
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397
hw/efinix_fpga/outflow/super6502.info.log Normal file
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///////////////////////////////////
// Efinity Synthesis Started
// Jun 09, 2022 21:36:12
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0010 VERI-ERROR] instantiating unknown module 'cpu_clk' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:92)
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 09, 2022 21:36:40
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0010 VERI-ERROR] instantiating unknown module 'memory_mapper' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:118)
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 09, 2022 21:42:28
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
[EFX-0012 VERI-INFO] compiling module 'sdram' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
[EFX-0012 VERI-INFO] module 'sdram' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 11, 2022 12:05:39
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
[EFX-0012 VERI-INFO] compiling module 'sdram' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
[EFX-0012 VERI-INFO] module 'sdram' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 11, 2022 19:19:40
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0010 VERI-ERROR] overwriting previous definition of module 'sdram' (VERI-1206) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:174)
[EFX-0012 VERI-INFO] previous definition of design element 'sdram' is here (VERI-2142) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:87)
[EFX-0010 VERI-ERROR] module 'axi4_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1006)
[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_wrapper_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1327)
[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1740)
[EFX-0010 VERI-ERROR] module 'efx_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2308)
[EFX-0010 VERI-ERROR] module 'sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2585)
[EFX-0010 VERI-ERROR] module 'sdram_fsm_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3419)
[EFX-0010 VERI-ERROR] module 'sdram_io_block_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3784)
[EFX-0010 VERI-ERROR] module 'sdram_simple_dual_port_ram_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3948)
[EFX-0010 VERI-ERROR] module 'sync_ddio_group_in_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4066)
[EFX-0010 VERI-ERROR] module 'sync_ddio_group_out_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4194)
///////////////////////////////////
// Efinity Synthesis Started
// Jun 11, 2022 19:20:04
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 11, 2022 19:20:55
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 11, 2022 19:21:29
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
[EFX-0012 VERI-INFO] compiling module 'sdram_adapter' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
[EFX-0012 VERI-INFO] module 'sdram_adapter' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 11, 2022 19:21:33
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
[EFX-0012 VERI-INFO] compiling module 'sdram_adapter' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
[EFX-0012 VERI-INFO] module 'sdram_adapter' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
///////////////////////////////////
// Efinity Synthesis Started
// Jun 13, 2022 19:05:46
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_GROUP', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_WIDTH', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
///////////////////////////////////
// Efinity Synthesis Started
// Jun 13, 2022 19:08:09
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_GROUP', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_WIDTH', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
///////////////////////////////////
// Efinity Synthesis Started
// Jun 13, 2022 19:08:21
///////////////////////////////////
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
[EFX-0011 VERI-WARNING] port 'i_sysclk' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'o_pll_reset' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.