From 673386f9f914aab45ddb1aaf501e42c27c5f0b88 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 12 Oct 2023 19:32:12 -0700 Subject: [PATCH 1/6] Change clk_2 to clk_cpu --- hw/efinix_fpga/simulation/src/sim_top.sv | 14 +++++++------- hw/efinix_fpga/src/super6502.sv | 24 ++++++++++++------------ 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv index 4d18031..474af69 100644 --- a/hw/efinix_fpga/simulation/src/sim_top.sv +++ b/hw/efinix_fpga/simulation/src/sim_top.sv @@ -4,7 +4,7 @@ module sim_top(); `include "include/super6502_sdram_controller_define.vh" -logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2; +logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu; // clk_100 initial begin @@ -30,11 +30,11 @@ initial begin end end -// clk_2 +// clk_cpu initial begin - r_clk_2 <= '1; + r_clk_cpu <= '1; forever begin - #250 r_clk_2 <= ~r_clk_2; + #250 r_clk_cpu <= ~r_clk_cpu; end end @@ -47,9 +47,9 @@ logic button_reset; initial begin button_reset <= '0; - repeat(10) @(r_clk_2); + repeat(10) @(r_clk_cpu); button_reset <= '1; - repeat(1000000) @(r_clk_2); + repeat(1000000) @(r_clk_cpu); $finish(); end @@ -101,7 +101,7 @@ super6502 u_dut( .i_sdrclk(r_sdrclk), .i_tACclk(~r_sdrclk), .clk_50(r_clk_50), - .clk_2(r_clk_2), + .clk_cpu(r_clk_cpu), .button_reset(button_reset), .cpu_resb(w_cpu_reset), .cpu_addr(w_cpu_addr), diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv index b0b1a49..5cdc894 100644 --- a/hw/efinix_fpga/src/super6502.sv +++ b/hw/efinix_fpga/src/super6502.sv @@ -11,7 +11,7 @@ module super6502 input button_reset, input pll_cpu_locked, input clk_50, - input clk_2, + input clk_cpu, input logic [15:0] cpu_addr, output logic [7:0] cpu_data_out, output logic [7:0] cpu_data_oe, @@ -56,11 +56,11 @@ assign cpu_nmib = '1; logic w_wait; assign cpu_rdy = ~w_wait; -assign cpu_phi2 = clk_2; +assign cpu_phi2 = clk_cpu; logic w_sdr_init_done; -always @(posedge clk_2) begin +always @(posedge clk_cpu) begin if (button_reset == '0) begin cpu_resb <= '0; end @@ -124,12 +124,12 @@ end rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom( .addr(cpu_addr[11:0]), - .clk(clk_2), + .clk(clk_cpu), .data(w_rom_data_out) ); leds u_leds( - .clk(clk_2), + .clk(clk_cpu), .i_data(cpu_data_in), .o_data(w_leds_data_out), .cs(w_leds_cs), @@ -140,7 +140,7 @@ leds u_leds( logic w_timer_irqb; timer u_timer( - .clk(clk_2), + .clk(clk_cpu), .reset(~cpu_resb), .i_data(cpu_data_in), .o_data(w_timer_data_out), @@ -151,7 +151,7 @@ timer u_timer( ); multiplier u_multiplier( - .clk(clk_2), + .clk(clk_cpu), .reset(~cpu_resb), .i_data(cpu_data_in), .o_data(w_multiplier_data_out), @@ -161,7 +161,7 @@ multiplier u_multiplier( ); divider_wrapper u_divider( - .clk(clk_2), + .clk(clk_cpu), .divclk(clk_50), .reset(~cpu_resb), .i_data(cpu_data_in), @@ -174,7 +174,7 @@ divider_wrapper u_divider( logic w_uart_irqb; uart_wrapper u_uart( - .clk(clk_2), + .clk(clk_cpu), .clk_50(clk_50), .reset(~cpu_resb), .i_data(cpu_data_in), @@ -188,7 +188,7 @@ uart_wrapper u_uart( ); spi_controller spi_controller( - .i_clk(clk_2), + .i_clk(clk_cpu), .i_rst(~cpu_resb), .i_cs(w_spi_cs), .i_rwb(cpu_rwb), @@ -204,7 +204,7 @@ spi_controller spi_controller( sdram_adapter u_sdram_adapter( - .i_cpuclk(clk_2), + .i_cpuclk(clk_cpu), .i_arst(~button_reset), .i_sysclk(i_sysclk), .i_sdrclk(i_sdrclk), @@ -234,7 +234,7 @@ sdram_adapter u_sdram_adapter( ); interrupt_controller u_interrupt_controller( - .clk(clk_2), + .clk(clk_cpu), .reset(~cpu_resb), .i_data(cpu_data_in), .o_data(w_irq_data_out), From afd8de92cc3f0061d6a917c162b08e37f7a31c04 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 13:12:46 -0700 Subject: [PATCH 2/6] Fix sdram wrapper state machine --- hw/efinix_fpga/simulation/src/sim_top.sv | 6 ++- hw/efinix_fpga/src/sdram_adapter.sv | 63 ++++++++++++++---------- 2 files changed, 41 insertions(+), 28 deletions(-) diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv index 474af69..98053fb 100644 --- a/hw/efinix_fpga/simulation/src/sim_top.sv +++ b/hw/efinix_fpga/simulation/src/sim_top.sv @@ -34,10 +34,14 @@ end initial begin r_clk_cpu <= '1; forever begin - #250 r_clk_cpu <= ~r_clk_cpu; + #125 r_clk_cpu <= ~r_clk_cpu; end end +initial begin + #275000 $finish(); +end + initial begin $dumpfile("sim_top.vcd"); $dumpvars(0,sim_top); diff --git a/hw/efinix_fpga/src/sdram_adapter.sv b/hw/efinix_fpga/src/sdram_adapter.sv index 9b0b7c0..deeccd9 100644 --- a/hw/efinix_fpga/src/sdram_adapter.sv +++ b/hw/efinix_fpga/src/sdram_adapter.sv @@ -70,7 +70,7 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2]; // But basically if we are in access, and cpuclk goes low, go back to wait. // If something actually happened, we would be in one of the read/write states. -enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state; +enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state; logic w_read, w_write, w_last; logic [23:0] w_addr, r_addr; @@ -86,21 +86,6 @@ logic [31:0] r_write_data; logic [1:0] counter, next_counter; -always @(posedge i_sysclk) begin - if (i_arst) begin - state <= WAIT; - counter <= '0; - end else begin - state <= next_state; - counter <= next_counter; - r_write_data <= w_data_i; - r_addr <= w_addr; - r_dm <= w_dm; - end - - if (w_data_valid) - o_data <= _data; -end logic r_wait; logic _r_wait; @@ -126,6 +111,20 @@ always @(posedge i_sysclk or posedge i_arst) begin end end end + + if (i_arst) begin + state <= WAIT; + counter <= '0; + end else begin + state <= next_state; + counter <= next_counter; + r_write_data <= w_data_i; + r_addr <= w_addr; + r_dm <= w_dm; + end + + if (w_data_valid) + o_data <= _data; end //because of timing issues, We really need to trigger @@ -178,26 +177,29 @@ always_comb begin ACCESS: begin // only do something if selected if (i_cs) begin - w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0 + w_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0 if (i_rwb) begin //read - w_read = '1; - w_last = '1; - // dm is not needed for reads? - if (w_rd_ack) next_state = READ_WAIT; + next_state = PRE_READ; end else begin //write w_data_i = i_data << (8*i_addr[1:0]); - //w_data_i = {4{i_data}}; //does anything get through? w_dm = ~(4'b1 << i_addr[1:0]); - if (~i_cpuclk) begin - w_write = '1; - w_last = '1; - next_state = WRITE_WAIT; - end + next_state = PRE_WRITE; end end end + PRE_WRITE: begin + w_data_i = r_write_data; + w_dm = r_dm; + //w_data_i = {4{i_data}}; //does anything get through? + if (~i_cpuclk) begin + w_write = '1; + w_last = '1; + next_state = WRITE_WAIT; + end + end + WRITE_WAIT: begin // stay in this state until write is acknowledged. w_write = '1; @@ -207,6 +209,13 @@ always_comb begin w_addr = r_addr; if (w_wr_ack) next_state = WAIT; end + + PRE_READ: begin + w_read = '1; + w_last = '1; + // dm is not needed for reads? + if (w_rd_ack) next_state = READ_WAIT; + end READ_WAIT: begin if (w_rd_valid) begin From 32f6c0f8d99c31180b00ebd7d2a7c429115ddff3 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 13:30:09 -0700 Subject: [PATCH 3/6] Add jsr test --- hw/efinix_fpga/simulation/src/sim_top.sv | 6 ++-- sw/Makefile | 4 +-- sw/test_code/jsr_test/Makefile | 39 ++++++++++++++++++++++++ sw/test_code/jsr_test/link.ld | 35 +++++++++++++++++++++ sw/test_code/jsr_test/main.s | 23 ++++++++++++++ sw/test_code/jsr_test/vectors.s | 14 +++++++++ 6 files changed, 116 insertions(+), 5 deletions(-) create mode 100644 sw/test_code/jsr_test/Makefile create mode 100644 sw/test_code/jsr_test/link.ld create mode 100644 sw/test_code/jsr_test/main.s create mode 100644 sw/test_code/jsr_test/vectors.s diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv index 98053fb..a01f70c 100644 --- a/hw/efinix_fpga/simulation/src/sim_top.sv +++ b/hw/efinix_fpga/simulation/src/sim_top.sv @@ -38,9 +38,9 @@ initial begin end end -initial begin - #275000 $finish(); -end +// initial begin +// #275000 $finish(); +// end initial begin $dumpfile("sim_top.vcd"); diff --git a/sw/Makefile b/sw/Makefile index a47ed42..ad99e40 100644 --- a/sw/Makefile +++ b/sw/Makefile @@ -17,6 +17,6 @@ kernel: clean: - @$(MAKE) -C bootloader --no-print-directory $@ + @$(MAKE) -C bios --no-print-directory $@ @$(MAKE) -C kernel --no-print-directory $@ - @$(MAKE) -C cc65 --no-print-directory $@ \ No newline at end of file + @$(MAKE) -C cc65 --no-print-directory $@ diff --git a/sw/test_code/jsr_test/Makefile b/sw/test_code/jsr_test/Makefile new file mode 100644 index 0000000..262a351 --- /dev/null +++ b/sw/test_code/jsr_test/Makefile @@ -0,0 +1,39 @@ +CC=../../cc65/bin/cl65 +LD=../../cc65/bin/cl65 +CFLAGS=-T -t none -I. --cpu "65C02" +LDFLAGS=-C link.ld -m $(NAME).map + +NAME=jsr_test + +BIN=$(NAME).bin +HEX=$(NAME).hex + +LISTS=lists + +SRCS=$(wildcard *.s) $(wildcard *.c) +SRCS+=$(wildcard **/*.s) $(wildcard **/*.c) +OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS))) +OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS))) + +# Make sure the kernel linked to correct address, no relocation! +all: $(HEX) + +$(HEX): $(BIN) + objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX) + +$(BIN): $(OBJS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@ + +%.o: %.c $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +%.o: %.s $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +$(LISTS): + mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS)))) + +.PHONY: clean +clean: + rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map + diff --git a/sw/test_code/jsr_test/link.ld b/sw/test_code/jsr_test/link.ld new file mode 100644 index 0000000..66a42fe --- /dev/null +++ b/sw/test_code/jsr_test/link.ld @@ -0,0 +1,35 @@ +MEMORY +{ + ZP: start = $0, size = $100, type = rw, define = yes; + SDRAM: start = $9200, size = $4d00, type = rw, define = yes; + ROM: start = $F000, size = $1000, file = %O; +} + +SEGMENTS { + ZEROPAGE: load = ZP, type = zp, define = yes; + DATA: load = ROM, type = rw, define = yes, run = SDRAM; + BSS: load = SDRAM, type = bss, define = yes; + HEAP: load = SDRAM, type = bss, optional = yes; + STARTUP: load = ROM, type = ro; + ONCE: load = ROM, type = ro, optional = yes; + CODE: load = ROM, type = ro; + RODATA: load = ROM, type = ro; + VECTORS: load = ROM, type = ro, start = $FFFA; +} + +FEATURES { + CONDES: segment = STARTUP, + type = constructor, + label = __CONSTRUCTOR_TABLE__, + count = __CONSTRUCTOR_COUNT__; + CONDES: segment = STARTUP, + type = destructor, + label = __DESTRUCTOR_TABLE__, + count = __DESTRUCTOR_COUNT__; +} + +SYMBOLS { + # Define the stack size for the application + __STACKSIZE__: value = $0200, type = weak; + __STACKSTART__: type = weak, value = $0800; # 2k stack +} diff --git a/sw/test_code/jsr_test/main.s b/sw/test_code/jsr_test/main.s new file mode 100644 index 0000000..4c74c59 --- /dev/null +++ b/sw/test_code/jsr_test/main.s @@ -0,0 +1,23 @@ +.export _init, _nmi_int, _irq_int + +.code + +_nmi_int: +_irq_int: + +_init: + ldx #$ff + txs + lda #$00 + jsr subroutine + sta $00 +@1: bra @1 + +subroutine: + inc + jsr suborutine2 + rts + +suborutine2: + inc + rts \ No newline at end of file diff --git a/sw/test_code/jsr_test/vectors.s b/sw/test_code/jsr_test/vectors.s new file mode 100644 index 0000000..81ae6e0 --- /dev/null +++ b/sw/test_code/jsr_test/vectors.s @@ -0,0 +1,14 @@ +; --------------------------------------------------------------------------- +; vectors.s +; --------------------------------------------------------------------------- +; +; Defines the interrupt vector table. + +.import _init +.import _nmi_int, _irq_int + +.segment "VECTORS" + +.addr _nmi_int ; NMI vector +.addr _init ; Reset vector +.addr _irq_int ; IRQ/BRK vector \ No newline at end of file From e0e20d7fb40344cfbfe934052dfeed92df51db18 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 13:37:13 -0700 Subject: [PATCH 4/6] Add indirect test --- sw/test_code/indirect_test/Makefile | 39 ++++++++++++++++++++++++++++ sw/test_code/indirect_test/link.ld | 35 +++++++++++++++++++++++++ sw/test_code/indirect_test/main.s | 20 ++++++++++++++ sw/test_code/indirect_test/vectors.s | 14 ++++++++++ 4 files changed, 108 insertions(+) create mode 100644 sw/test_code/indirect_test/Makefile create mode 100644 sw/test_code/indirect_test/link.ld create mode 100644 sw/test_code/indirect_test/main.s create mode 100644 sw/test_code/indirect_test/vectors.s diff --git a/sw/test_code/indirect_test/Makefile b/sw/test_code/indirect_test/Makefile new file mode 100644 index 0000000..5fbaadc --- /dev/null +++ b/sw/test_code/indirect_test/Makefile @@ -0,0 +1,39 @@ +CC=../../cc65/bin/cl65 +LD=../../cc65/bin/cl65 +CFLAGS=-T -t none -I. --cpu "65C02" +LDFLAGS=-C link.ld -m $(NAME).map + +NAME=indirect_test + +BIN=$(NAME).bin +HEX=$(NAME).hex + +LISTS=lists + +SRCS=$(wildcard *.s) $(wildcard *.c) +SRCS+=$(wildcard **/*.s) $(wildcard **/*.c) +OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS))) +OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS))) + +# Make sure the kernel linked to correct address, no relocation! +all: $(HEX) + +$(HEX): $(BIN) + objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX) + +$(BIN): $(OBJS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@ + +%.o: %.c $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +%.o: %.s $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +$(LISTS): + mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS)))) + +.PHONY: clean +clean: + rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map + diff --git a/sw/test_code/indirect_test/link.ld b/sw/test_code/indirect_test/link.ld new file mode 100644 index 0000000..66a42fe --- /dev/null +++ b/sw/test_code/indirect_test/link.ld @@ -0,0 +1,35 @@ +MEMORY +{ + ZP: start = $0, size = $100, type = rw, define = yes; + SDRAM: start = $9200, size = $4d00, type = rw, define = yes; + ROM: start = $F000, size = $1000, file = %O; +} + +SEGMENTS { + ZEROPAGE: load = ZP, type = zp, define = yes; + DATA: load = ROM, type = rw, define = yes, run = SDRAM; + BSS: load = SDRAM, type = bss, define = yes; + HEAP: load = SDRAM, type = bss, optional = yes; + STARTUP: load = ROM, type = ro; + ONCE: load = ROM, type = ro, optional = yes; + CODE: load = ROM, type = ro; + RODATA: load = ROM, type = ro; + VECTORS: load = ROM, type = ro, start = $FFFA; +} + +FEATURES { + CONDES: segment = STARTUP, + type = constructor, + label = __CONSTRUCTOR_TABLE__, + count = __CONSTRUCTOR_COUNT__; + CONDES: segment = STARTUP, + type = destructor, + label = __DESTRUCTOR_TABLE__, + count = __DESTRUCTOR_COUNT__; +} + +SYMBOLS { + # Define the stack size for the application + __STACKSIZE__: value = $0200, type = weak; + __STACKSTART__: type = weak, value = $0800; # 2k stack +} diff --git a/sw/test_code/indirect_test/main.s b/sw/test_code/indirect_test/main.s new file mode 100644 index 0000000..65cf841 --- /dev/null +++ b/sw/test_code/indirect_test/main.s @@ -0,0 +1,20 @@ +.export _init, _nmi_int, _irq_int + +.code + +_nmi_int: +_irq_int: + +_init: + ldx #$ff + txs + + lda #$aa + sta $01 + lda #$bb + sta $00 + ldy #$1 + lda #$cc + sta ($00),y + +@end: bra @end \ No newline at end of file diff --git a/sw/test_code/indirect_test/vectors.s b/sw/test_code/indirect_test/vectors.s new file mode 100644 index 0000000..81ae6e0 --- /dev/null +++ b/sw/test_code/indirect_test/vectors.s @@ -0,0 +1,14 @@ +; --------------------------------------------------------------------------- +; vectors.s +; --------------------------------------------------------------------------- +; +; Defines the interrupt vector table. + +.import _init +.import _nmi_int, _irq_int + +.segment "VECTORS" + +.addr _nmi_int ; NMI vector +.addr _init ; Reset vector +.addr _irq_int ; IRQ/BRK vector \ No newline at end of file From 362c9f140fc625b9fe213b275fe92e6f350cbc54 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 13:52:55 -0700 Subject: [PATCH 5/6] Fix synthesis issue --- hw/efinix_fpga/src/sdram_adapter.sv | 12 +- hw/efinix_fpga/super6502.xml | 167 ++++++++++++++-------------- 2 files changed, 93 insertions(+), 86 deletions(-) diff --git a/hw/efinix_fpga/src/sdram_adapter.sv b/hw/efinix_fpga/src/sdram_adapter.sv index deeccd9..c3c7822 100644 --- a/hw/efinix_fpga/src/sdram_adapter.sv +++ b/hw/efinix_fpga/src/sdram_adapter.sv @@ -86,6 +86,7 @@ logic [31:0] r_write_data; logic [1:0] counter, next_counter; +logic [7:0] o_data_next; logic r_wait; logic _r_wait; @@ -122,9 +123,8 @@ always @(posedge i_sysclk or posedge i_arst) begin r_addr <= w_addr; r_dm <= w_dm; end - - if (w_data_valid) - o_data <= _data; + + o_data <= o_data_next; end //because of timing issues, We really need to trigger @@ -167,6 +167,12 @@ always_comb begin w_data_i = '0; w_data_valid = '0; _data = 0; + + if (w_data_valid) begin + o_data_next = _data; + end else begin + o_data_next = o_data; + end unique case (state) WAIT: begin diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 1431efd..55c88b1 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,105 +1,106 @@ - + + - - - + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - + + - - + + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - \ No newline at end of file + From e768b245bd02d066a410028fd82382eccf984062 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 18:24:19 -0700 Subject: [PATCH 6/6] rework state machine --- hw/efinix_fpga/src/sdram_adapter.sv | 52 +++++++++++++++++------------ 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/hw/efinix_fpga/src/sdram_adapter.sv b/hw/efinix_fpga/src/sdram_adapter.sv index c3c7822..be3c816 100644 --- a/hw/efinix_fpga/src/sdram_adapter.sv +++ b/hw/efinix_fpga/src/sdram_adapter.sv @@ -73,7 +73,8 @@ assign o_sdr_DQM = w_sdr_DQM[0+:2]; enum bit [2:0] {ACCESS, PRE_READ, READ_WAIT, PRE_WRITE, WRITE_WAIT, WAIT} state, next_state; logic w_read, w_write, w_last; -logic [23:0] w_addr, r_addr; +logic [23:0] w_read_addr, w_write_addr; +logic [23:0] r_read_addr, r_write_addr; logic [31:0] w_data_i, w_data_o; logic [3:0] w_dm, r_dm; @@ -88,9 +89,13 @@ logic [1:0] counter, next_counter; logic [7:0] o_data_next; +logic [23:0] addr_mux_out; + +logic slow_mem; + logic r_wait; logic _r_wait; -assign o_wait = r_wait & i_cs; +assign o_wait = (r_wait | slow_mem) & i_cs; // we need to assert rdy low until a falling edge if a reset happens @@ -120,7 +125,8 @@ always @(posedge i_sysclk or posedge i_arst) begin state <= next_state; counter <= next_counter; r_write_data <= w_data_i; - r_addr <= w_addr; + r_read_addr <= w_read_addr; + r_write_addr <= w_write_addr; r_dm <= w_dm; end @@ -156,10 +162,12 @@ end always_comb begin + slow_mem = '0; next_state = state; next_counter = counter; - w_addr = '0; + w_read_addr = '0; + w_write_addr = '0; w_dm = '0; w_read = '0; w_write = '0; @@ -167,24 +175,19 @@ always_comb begin w_data_i = '0; w_data_valid = '0; _data = 0; - - if (w_data_valid) begin - o_data_next = _data; - end else begin - o_data_next = o_data; - end unique case (state) WAIT: begin - if (i_cs & i_cpuclk) + if (i_cs & ~i_cpuclk) next_state = ACCESS; end ACCESS: begin // only do something if selected if (i_cs) begin - w_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0 - + w_read_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0 + w_write_addr = {{i_addr[24:2]}, {1'b0}}; // divide by 2, set last bit to 0 + addr_mux_out = w_read_addr; if (i_rwb) begin //read next_state = PRE_READ; end else begin //write @@ -197,6 +200,8 @@ always_comb begin PRE_WRITE: begin w_data_i = r_write_data; + w_write_addr = r_write_addr; + addr_mux_out = w_write_addr; w_dm = r_dm; //w_data_i = {4{i_data}}; //does anything get through? if (~i_cpuclk) begin @@ -208,43 +213,46 @@ always_comb begin WRITE_WAIT: begin // stay in this state until write is acknowledged. + w_write_addr = r_write_addr; + addr_mux_out = w_write_addr; w_write = '1; w_last = '1; w_data_i = r_write_data; w_dm = r_dm; - w_addr = r_addr; if (w_wr_ack) next_state = WAIT; end PRE_READ: begin + w_read_addr = r_read_addr; + addr_mux_out = w_read_addr; w_read = '1; w_last = '1; + slow_mem = '1; // dm is not needed for reads? if (w_rd_ack) next_state = READ_WAIT; end READ_WAIT: begin + w_read_addr = r_read_addr; + addr_mux_out = w_read_addr; + slow_mem = '1; if (w_rd_valid) begin w_data_valid = '1; _data = w_data_o[8*i_addr[1:0]+:8]; end // you must wait until the next cycle! - if (~i_cpuclk) begin + if (w_data_valid) begin next_state = WAIT; end end endcase -end -//this seems scuffed -logic [23:0] addr_mux_out; -always_comb begin - if (state == ACCESS) begin - addr_mux_out = w_addr; + if (w_data_valid) begin + o_data_next = _data; end else begin - addr_mux_out = r_addr; + o_data_next = o_data; end end