From ff78fd0179a69d4f40e97018ee8a96b3adf8450b Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Mon, 14 Mar 2022 11:53:45 -0500 Subject: [PATCH] Connect Button 1 to cpu_irqb A maskable interrupt can be generated by pressing button 1, the reset button remains button 0. --- hw/fpga/super6502.qsf | 4 ++-- hw/fpga/super6502.sv | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf index 496716f..258c17c 100644 --- a/hw/fpga/super6502.qsf +++ b/hw/fpga/super6502.qsf @@ -101,7 +101,6 @@ set_location_assignment PIN_A13 -to SW[6] set_location_assignment PIN_A14 -to SW[7] set_location_assignment PIN_B14 -to SW[8] set_location_assignment PIN_F15 -to SW[9] -set_location_assignment PIN_A7 -to Run set_location_assignment PIN_A8 -to LED[0] set_location_assignment PIN_A9 -to LED[1] set_location_assignment PIN_A10 -to LED[2] @@ -272,7 +271,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Run set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] @@ -283,4 +281,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[9] +set_location_assignment PIN_A7 -to button_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to button_1 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index 54bcf61..37f7178 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -2,6 +2,7 @@ module super6502( input clk_50, input logic rst_n, + input logic button_1, input logic [15:0] cpu_addr, inout logic [7:0] cpu_data, @@ -61,7 +62,7 @@ assign cpu_sob = '0; assign cpu_resb = rst_n; assign cpu_be = '1; assign cpu_nmib = '1; -assign cpu_irqb = '1; +assign cpu_irqb = button_1; addr_decode decode( .addr(cpu_addr),