3 Commits

Author	SHA1	Message	Date
Byron Lathi	15e3ae9688	Add SDRAM controller (controller) ... Turns out there are some issues with holding the chip select for the SDRAM controller high for too long, so there is a simple 2-state fsm which ensures that the chip select is only held for 1 clock cycle for writes and for as long as it takes to read the data from sdram for reads.	2022-03-17 13:31:56 -05:00
Byron Lathi	3d9d340520	Get the FPGA part working ... This changes some of the clocks, fixes a bug in the seven segment stuff.	2022-03-11 22:55:26 -06:00
Byron Lathi	aca17a9cf8	Create quartus project	2022-03-05 17:52:42 -06:00