Byron Lathi
|
ac5564d03d
|
Add test program for mapper, fix reset bug
|
2023-10-20 08:27:51 -07:00 |
|
Byron Lathi
|
5a8d15de94
|
Refactor for FPGA synthesis
|
2023-10-19 18:57:42 -07:00 |
|
Byron Lathi
|
03456607c9
|
Route all addresses through mapper
|
2023-10-19 18:34:39 -07:00 |
|
Byron Lathi
|
69e443d223
|
Add mapped address output and test
|
2023-10-18 08:54:23 -07:00 |
|
Byron Lathi
|
35d4ea968e
|
Update testbench, fix off by 1
|
2023-10-18 08:40:00 -07:00 |
|
Byron Lathi
|
e621d4047b
|
Add mapper and testbench
|
2023-10-16 23:45:33 -07:00 |
|
Byron Lathi
|
360eecf3ca
|
Revert super6502 back to before mapper
|
2023-10-15 21:48:03 -07:00 |
|
Byron Lathi
|
a7b7f4fe35
|
Update build
|
2023-10-15 21:27:11 -07:00 |
|
Byron Lathi
|
155e89240a
|
Merge from master
|
2023-10-15 18:58:25 -07:00 |
|
Byron Lathi
|
e768b245bd
|
rework state machine
|
2023-10-15 18:24:19 -07:00 |
|
Byron Lathi
|
362c9f140f
|
Fix synthesis issue
|
2023-10-15 13:52:55 -07:00 |
|
Byron Lathi
|
afd8de92cc
|
Fix sdram wrapper state machine
|
2023-10-15 13:12:46 -07:00 |
|
Byron Lathi
|
673386f9f9
|
Change clk_2 to clk_cpu
|
2023-10-12 19:32:12 -07:00 |
|
Byron Lathi
|
4925354f53
|
Fix uart status multiple drivers
|
2023-09-27 23:02:53 -07:00 |
|
Byron Lathi
|
9e19a1eb72
|
Disable sdr debug, initialize uart status
|
2023-09-27 21:14:09 -07:00 |
|
Byron Lathi
|
c2dd5d616b
|
Gate rdy behind sdram_cs #28
|
2023-09-25 23:45:23 -07:00 |
|
Byron Lathi
|
bc0ab7eb54
|
Fix infinite loop
|
2023-09-22 19:46:25 -07:00 |
|
Byron Lathi
|
1f503b2d80
|
update sim environment
|
2023-09-21 20:35:52 -07:00 |
|
Byron Lathi
|
76aea3180a
|
Move mapper into src folder
|
2023-09-18 23:00:27 -07:00 |
|
Byron Lathi
|
66bebf476e
|
Merge from master
|
2023-09-18 20:08:59 -07:00 |
|
Byron Lathi
|
c466c62969
|
Resolve "Organize Project Better"
|
2023-09-19 02:57:26 +00:00 |
|