Byron Lathi
6bf7fee64b
Increase TCP count to 2
...
After removing all the inferred latches, we have enough space to have 2
TCP streams instead of just 1. Also we have way more timing slack.
Lesson learned, inferred latches are *really* bad and you should remove
them first before anything else.
2024-10-13 20:01:37 -07:00
Byron Lathi
5e8d91be53
Remove inferred latches
2024-10-13 19:50:02 -07:00
Byron Lathi
6265a8090c
Big update to try and pass timing. reduces tcp streams to 1
2024-10-13 18:43:12 -07:00
Byron Lathi
19e4344374
Make synthesis optional
2024-09-22 23:49:41 -07:00
Byron Lathi
40fe95ea0a
Add checksum calc to fpga sources
2024-09-14 15:26:22 -07:00
Byron Lathi
812cb6447a
Add mii clocks to constraints
2024-09-09 23:18:56 -07:00
Byron Lathi
8be97b45ae
Move to 4 TCP units for synthesis
...
Otherwise it does not fit in the T20
2024-09-09 22:59:59 -07:00
Byron Lathi
4612acbc4a
Synthesis 1
2024-09-09 22:02:39 -07:00
Byron Lathi
dc90c00172
Mega commit to kick things off
2024-09-01 22:23:21 -07:00
Byron Lathi
7b5fb1a682
Pass synthesis
2024-08-19 23:17:23 -07:00
Byron Lathi
b11be44446
Changes for synthesis
2024-08-19 23:09:32 -07:00
Byron Lathi
063f219f01
Add ntw files to project
2024-08-18 10:13:15 -07:00
Byron Lathi
434fc1b28a
Fix sdspi, add missing source file
2024-07-31 22:02:47 -07:00
Byron Lathi
e0f511df2e
Add new DMA files to project config
2024-07-26 23:02:40 -07:00
Byron Lathi
abb1668f14
Synthesis file updates
2024-07-20 21:51:28 -07:00
Byron Lathi
f126e383a3
Update SD stuff
2024-07-20 16:03:06 -07:00
Byron Lathi
bdb3fc96d6
Add new sd wrapper
...
Wrapper is neccesary for the address offset and also because the
controller will trigger on reads/writes to registers, but we need access
to each byte of the 32 bit registers.
The wrapper will need to somehow chose when to actually trigger the
controller, maybe by having shadow registers?
2024-07-17 21:18:13 -07:00
Byron Lathi
63edbff30f
Reset renaming, set card_detect
2024-07-17 00:43:30 -07:00
Byron Lathi
6b7f7837dd
Use ZipCPU SD controller
...
I trust it more than the other one
2024-07-17 00:17:24 -07:00
Byron Lathi
e0bf1580b6
First pass at integrating sd controller
2024-07-16 18:57:57 -07:00
Byron Lathi
4f152623a0
Remove all traces of old sd controller
2024-07-16 00:03:13 -07:00
Byron Lathi
25f51deaa7
Synthesize sd card dma
2024-03-17 22:26:42 -07:00
Byron Lathi
02097ff3b8
Update sd controller with data host
2024-03-12 20:23:41 -07:00
Byron Lathi
d3914b3a51
Add sd io pins
2024-03-10 16:09:12 -07:00
Byron Lathi
cb426670cd
Do synthesis with sd controller
2024-03-10 12:29:08 -07:00
Byron Lathi
358dfdbe75
Add sdram io to fpga
2024-03-03 23:31:02 -08:00
Byron Lathi
10a72d8e1f
Add sdram, don't think it works though
2024-03-03 20:43:37 -08:00
Byron Lathi
01b1ecbcac
Add basic sim
2024-03-03 17:09:17 -08:00
Byron Lathi
ab9da189d1
Build software correctly, ignore debugger files
2024-03-03 14:50:40 -08:00
Byron Lathi
42fbc17a2a
Add test code and top level Makefile
2024-03-03 12:52:44 -08:00
Byron Lathi
0752220b0e
Add basic project with cpu, ram and rom
2024-03-02 22:46:48 -08:00
