Byron Lathi
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766fe72daf
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add fin
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2024-09-28 00:20:51 -07:00 |
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Byron Lathi
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247033ea2d
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Uncomment module load
oops
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2024-09-01 22:26:39 -07:00 |
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Byron Lathi
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dc90c00172
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Mega commit to kick things off
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2024-09-01 22:23:21 -07:00 |
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Byron Lathi
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8208bd6fa5
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Use sram instead of sdram in sim, fully switch to verilator
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2024-08-18 10:04:54 -07:00 |
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Byron Lathi
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9b2a40df06
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Add tcp regs and switch to verilator
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2024-08-17 11:56:01 -07:00 |
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Byron Lathi
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5cd03a37eb
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Start working on axi dma
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2024-07-22 00:07:04 -07:00 |
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Byron Lathi
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08717235a8
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Also load iverilog module
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2024-07-15 23:59:01 -07:00 |
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Byron Lathi
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991cd24e73
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Change to using modules
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2024-07-15 22:39:27 -07:00 |
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Byron Lathi
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142759ff59
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Require python3.11
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2024-03-10 16:42:21 -07:00 |
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Byron Lathi
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8f6d074255
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Re-order init script to fix python import issue in synthesis
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2024-03-10 12:55:38 -07:00 |
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Byron Lathi
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a343b23ddd
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Make a venv in build
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2024-03-03 13:13:41 -08:00 |
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Byron Lathi
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b9595a7450
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Create project, set env vars
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2023-11-26 17:08:30 -08:00 |
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Byron Lathi
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f8bdbfbb2b
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Resolve "Run simulation as part of ci"
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2023-09-30 05:05:12 +00:00 |
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Byron Lathi
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3fcfa4d3ac
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Add REPO_TOP env var
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2023-09-24 10:35:17 -07:00 |
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