Byron Lathi
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cc32430f2a
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Refactor makefile, update verilog-sd-emulator
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2023-09-29 23:48:28 -07:00 |
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Byron Lathi
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913351efd4
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Add sd emulator as submodule
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2023-09-28 23:09:47 -07:00 |
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Byron Lathi
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62967aa88d
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Resolve "Add build check to CI"
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2023-09-29 05:14:52 +00:00 |
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Byron Lathi
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4d0abbb508
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Add sim uart
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2023-09-27 22:15:27 -07:00 |
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Byron Lathi
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9e19a1eb72
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Disable sdr debug, initialize uart status
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2023-09-27 21:14:09 -07:00 |
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Byron Lathi
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ec4c3bab86
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Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
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2023-09-26 23:15:22 -07:00 |
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Byron Lathi
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915188e8f1
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New test program that causes the error
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2023-09-26 18:23:01 -07:00 |
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Byron Lathi
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c2dd5d616b
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Gate rdy behind sdram_cs #28
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2023-09-25 23:45:23 -07:00 |
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Byron Lathi
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4ee21f23b6
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Up the sim time
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2023-09-25 19:13:06 -07:00 |
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Byron Lathi
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95e05292cc
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Fix clocks, define RTL_SIM
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2023-09-24 23:58:32 -07:00 |
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Byron Lathi
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be68b4c9f9
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Change sdrclk and sysclk to have aligned rising edges
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2023-09-24 14:53:38 -07:00 |
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Byron Lathi
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3fcfa4d3ac
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Add REPO_TOP env var
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2023-09-24 10:35:17 -07:00 |
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Byron Lathi
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9bd031e35e
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Add support for test programs
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2023-09-24 10:29:32 -07:00 |
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Byron Lathi
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13ea5ca71b
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Add memory
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2023-09-24 10:06:23 -07:00 |
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Byron Lathi
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d3aa195adf
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Add updated sim cpu with fix
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2023-09-23 10:49:44 -07:00 |
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Byron Lathi
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00173f4e89
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Add submodule back
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2023-09-23 09:59:39 -07:00 |
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Byron Lathi
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77dd4f1002
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remove sim submodule
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2023-09-23 09:59:09 -07:00 |
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Byron Lathi
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bc0ab7eb54
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Fix infinite loop
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2023-09-22 19:46:25 -07:00 |
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Byron Lathi
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5e03795c09
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Get something simulated
Infinite loop being caused somewhere
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2023-09-21 23:22:17 -07:00 |
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Byron Lathi
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1f503b2d80
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update sim environment
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2023-09-21 20:35:52 -07:00 |
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Byron Lathi
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e50203dd3e
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Add generic SDR
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2023-09-21 19:23:31 -07:00 |
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Byron Lathi
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d37e32ec64
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Add sim cpu
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2023-09-18 23:27:54 -07:00 |
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Byron Lathi
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5ca5fca29b
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Get SD card working in SPI
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2023-07-23 14:55:14 -07:00 |
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Byron Lathi
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6a1a76db35
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Implement basic SPI controller
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2023-07-21 23:01:37 -07:00 |
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Byron Lathi
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85f12c75f1
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Start spi controller and tb
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2023-07-21 22:10:39 -07:00 |
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Byron Lathi
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9a2f0a4bb4
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Create interrupt controller
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2023-01-03 14:50:45 -05:00 |
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Byron Lathi
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34afd3875c
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Add timer and testbench
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2022-12-29 11:14:32 -05:00 |
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