Byron Lathi
c466c62969
Resolve "Organize Project Better"
2023-09-19 02:57:26 +00:00
Byron Lathi
b2b3b84bc4
Kernel crashing
2023-08-26 23:15:36 +00:00
Byron Lathi
eba24c2990
Disable inits which fail
2023-08-26 13:42:06 -07:00
Byron Lathi
0247565f49
Get super simple kernel code running
2023-08-26 13:09:02 -07:00
Byron Lathi
fd9389268a
Load root directory from sd card
2023-08-12 16:09:03 -07:00
Byron Lathi
e73c4e1d08
Rewrite readblock in assembly
2023-08-08 19:28:10 -07:00
Byron Lathi
709c60cf36
SD_command assembly rewrite
2023-07-23 16:25:13 -07:00
Byron Lathi
5ca5fca29b
Get SD card working in SPI
2023-07-23 14:55:14 -07:00
Byron Lathi
21e3a477c1
Update IP
2023-07-19 21:06:20 -07:00
Byron Lathi
7682dffe3c
Change test program to use correct args
...
Seems to work, when you run the test program it resets the card and
sends the voltage and test pattern, and it does receive a response from
the card.
2023-01-12 21:45:13 -06:00
Byron Lathi
98c07b59b4
Add files from previous version
2023-01-12 17:06:25 -06:00
Byron Lathi
519cd19739
Add uart2 test program
...
Reads input from uart and then writes it back out again immediately.
2023-01-12 14:05:13 -06:00
Byron Lathi
ab46236816
First throw at UART.
2023-01-12 13:34:46 -06:00
Byron Lathi
7e97784992
Create UART and uart_wrapper
2023-01-11 21:16:16 -05:00
Byron Lathi
8181a3a583
Change divider to pipelined version
...
The pipelining allows the cpu to run at a faster clock speed but results
in latency. At the current 2 MHz, there is 1 cycle of latency which is
negligible because the 6502 cannot do sequential data memory accesses.
In the future, there will have to be some sort of status flag or
interrupt showing that the divider is ready.
2023-01-05 19:21:00 -05:00
Byron Lathi
5f6657a227
Add divider
...
Adds a 16x16 divider to go with the multiplier.
The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.
This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.
2023-01-05 18:35:42 -05:00
Byron Lathi
42ad901ba4
Add multiplier
...
Add 16x16 multiplier.
Pretty simple. Address 0-1 is multipled by address 2-3 and the result is
in address 4-7, all little endian of course.
2023-01-04 16:15:02 -05:00
Byron Lathi
32a78a4aff
Add interrupt based timer and test code
2023-01-03 18:20:34 -05:00
Byron Lathi
1ac3bdf614
update timer
...
change how timer works, now counter and timer are not separate.
2023-01-03 15:49:56 -05:00
Byron Lathi
9a2f0a4bb4
Create interrupt controller
2023-01-03 14:50:45 -05:00
Byron Lathi
8c4102612f
Add timer and test program
2022-12-29 11:51:38 -05:00
Byron Lathi
91833e1f4f
Test the runram program
2022-12-23 14:35:45 -05:00
Byron Lathi
6361f39e0b
Add back in DM signals for proper byte accesses
2022-12-22 23:26:01 -05:00
Byron Lathi
e08e839d01
New test program
2022-12-22 22:39:43 -05:00
Byron Lathi
cf9aef64ac
First stab at getting sdram working
2022-12-22 20:25:32 -05:00
Byron Lathi
b8161e3082
Add LED module and address decoding; disable LA
...
The Logic analyzer isn't that useful anyway since it does not track
rising and falling edges.
2022-12-20 19:26:24 -05:00
Byron Lathi
12fb6283cc
Get block rom working
2022-12-20 17:26:59 -05:00
Byron Lathi
52de8d3eb3
Get block rom kind of working
2022-12-20 15:38:55 -05:00
Byron Lathi
19b13164e9
RWB and ADDR are inputs, not outputs!
2022-12-19 23:43:45 -05:00
Byron Lathi
09e31fe7ab
Start over pretty much.
2022-12-19 23:12:22 -05:00
