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base: bslathi19:98-new-dev-board
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bslathi19:master bslathi19:102-new-bootloader bslathi19:101-new-kernel bslathi19:AXI-Rewrite bslathi19:main bslathi19:100-support-sending-fin bslathi19:97-calculate-checksum-for-tcp-data-also bslathi19:99-respond-to-fin-packet bslathi19:wtf bslathi19:98-new-dev-board
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compare: bslathi19:wtf
Branches Tags
bslathi19:102-new-bootloader bslathi19:101-new-kernel bslathi19:AXI-Rewrite bslathi19:main bslathi19:master bslathi19:100-support-sending-fin bslathi19:97-calculate-checksum-for-tcp-data-also bslathi19:99-respond-to-fin-packet bslathi19:wtf bslathi19:98-new-dev-board

1 Commits
98-new-dev ... wtf

Author SHA1 Message Date
Byron Lathi
bb360d3c6d add fin 2024-09-28 00:17:45 -07:00
17 changed files with 696 additions and 96111 deletions
Expand all files Collapse all files

35
.gitignore vendored
View File

@@ -23,38 +23,3 @@ sim_top
# Allow sources.list specifically
!*sources.list
# For PCBs designed using KiCad: https://www.kicad.org/
# Format documentation: https://kicad.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*-backups
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
\#auto_saved_files\#
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
gerbers*

3
.gitmodules vendored
View File

@@ -13,6 +13,3 @@
[submodule "hw/super6502_fpga/src/sub/sdspi"]
path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi
url = ../sdspi.git
[submodule "hw/kicad_library"]
path = hw/kicad_library
url = ../kicad_library.git

2
hw/T120F484_dev/T120F484_dev.kicad_pcb
View File

@@ -1,2 +0,0 @@
(kicad_pcb (version 20240108) (generator "pcbnew") (generator_version "8.0")
)

635
hw/T120F484_dev/T120F484_dev.kicad_pro
View File

@@ -1,635 +0,0 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "T120F484_dev.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.127,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3048,
"microvia_drill": 0.1016,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.6096,
"via_drill": 0.3048,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": false,
"label": "#",
"name": "${ITEM_NUMBER}",
"show": false
},
{
"group_by": false,
"label": "Digikey",
"name": "Digikey",
"show": true
},
{
"group_by": false,
"label": "Description",
"name": "Description",
"show": false
}
],
"filter_string": "",
"group_symbols": true,
"name": "",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"375df3e3-db42-4b01-a9b9-2a249a6445e6",
"Root"
],
[
"f085d9c0-aa96-4d9d-ba76-31038a6b4413",
"fpga_power"
],
[
"4b6a0d07-8936-411b-9846-64d6ef0783de",
"config"
],
[
"ccc94dcb-e18b-43e8-8734-8b400da79052",
"power"
],
[
"94e15953-1e80-4b12-b1f3-c9e680581b64",
"clock"
],
[
"fffcc102-91a1-4cf0-a84c-ddfbd535f5ae",
"ddr"
]
],
"text_variables": {}
}

33813
hw/T120F484_dev/T120F484_dev.kicad_sch
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File diff suppressed because it is too large Load Diff

16329
hw/T120F484_dev/clock.kicad_sch
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File diff suppressed because it is too large Load Diff

19697
hw/T120F484_dev/config.kicad_sch
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File diff suppressed because it is too large Load Diff

10741
hw/T120F484_dev/ddr.kicad_sch
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File diff suppressed because it is too large Load Diff

14839
hw/T120F484_dev/fpga_power.kicad_sch
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File diff suppressed because it is too large Load Diff

8
hw/T120F484_dev/power.kicad_sch
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@@ -1,8 +0,0 @@
(kicad_sch
(version 20231120)
(generator "eeschema")
(generator_version "8.0")
(uuid "f0b5a570-6b3a-4b35-be20-fe5ec6a7ec52")
(paper "A3")
(lib_symbols)
)

1
hw/kicad_library

Submodule hw/kicad_library deleted from f1eb70654a

270
hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/scapy_irl_test.py Normal file
View File

@@ -0,0 +1,270 @@
from http import server
from scapy.layers.inet import Ether, IP, TCP
from scapy.layers.l2 import ARP
from scapy.data import IP_PROTOS
from scapy import sendrecv
from scapy.config import conf
from scapy.supersocket import L3RawSocket
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import Timer
from cocotb.triggers import RisingEdge
from cocotbext.axi import AxiLiteBus, AxiLiteMaster, AxiLiteRam
from cocotbext.eth import MiiPhy, GmiiFrame
import struct
from scapy.layers.inet import Ether, IP, TCP
from scapy.layers.l2 import ARP
from scapy.utils import PcapWriter
from scapy.layers.tuntap import TunTapInterface
import logging
from decimal import Decimal
CLK_PERIOD_NS = 10
MII_CLK_PERIOD_NS = 40
import socket
# In order for this to work, you need to run these commands:
# sudo ip tuntap add name tun0 mode tun user $USER
# sudo ip a add 172.0.0.1 peer 172.0.0.2 dev tun0
# sudo ip link set tun0 up
def main():
serversocket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
serversocket.bind(("172.0.0.1", 5678))
serversocket.listen(5)
t = TunTapInterface('tun0')
tcp_syn = IP(src="172.0.0.2", dst="172.0.0.1")/TCP(sport=1234, dport=5678, seq=0, ack=0, flags="S")
t.send(tcp_syn)
pkt = t.recv()
print(pkt)
if __name__ == "__main__":
main()
class TB:
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, CLK_PERIOD_NS, units="ns").start())
cocotb.start_soon(Clock(dut.mii_rx_clk, MII_CLK_PERIOD_NS, units="ns").start())
cocotb.start_soon(Clock(dut.mii_tx_clk, MII_CLK_PERIOD_NS, units="ns").start())
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_regs_axil"), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_prefix(dut, "m_dma_axil"), dut.clk, dut.rst, size=2**16)
self.mii_phy = MiiPhy(dut.mii_txd, dut.mii_tx_er, dut.mii_tx_en, dut.mii_tx_clk,
dut.mii_rxd, dut.mii_rx_er, dut.mii_rx_dv, dut.mii_rx_clk, None, speed=100e6)
async def cycle_reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk) # type: ignore
await RisingEdge(self.dut.clk) # type: ignore
self.dut.rst.value = 1
await RisingEdge(self.dut.clk) # type: ignore
await RisingEdge(self.dut.clk) # type: ignore
self.dut.rst.value = 0
await RisingEdge(self.dut.clk) # type: ignore
await RisingEdge(self.dut.clk) # type: ignore
def ip_to_hex(ip: str) -> int:
octets = [int(i) for i in ip.split(".")]
result = int.from_bytes(struct.pack("BBBB", octets[0], octets[1], octets[2], octets[3]))
return result
@cocotb.test()
async def test_irl(dut):
tb = TB(dut)
await tb.cycle_reset()
dut_ip = "172.0.0.2"
tb_ip = "172.0.0.1"
tb_mac = "02:00:00:11:22:33"
serversocket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
serversocket.bind((tb_ip, 5678))
serversocket.listen(5)
t = TunTapInterface('tun0')
dut_port = 1234
tb_port = 5678
await tb.axil_master.write_dword(0x0, 0x1807)
await tb.axil_master.write_dword(0x200, dut_port)
await tb.axil_master.write_dword(0x204, ip_to_hex(dut_ip))
await tb.axil_master.write_dword(0x208, tb_port)
await tb.axil_master.write_dword(0x20c, ip_to_hex(tb_ip))
await tb.axil_master.write_dword(0x210, 0x3)
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
tb.log.info(f"Packet Type: {packet.type:x}")
assert packet.type == 0x806, "Packet type is not ARP!"
arp_request = packet.payload
assert isinstance(arp_request, ARP)
tb.log.info(f"Arp OP: {arp_request.op}")
tb.log.info(f"Arp hwsrc: {arp_request.hwsrc}")
tb.log.info(f"Arp hwdst: {arp_request.hwdst}")
tb.log.info(f"Arp psrc: {arp_request.psrc}")
tb.log.info(f"Arp pdst: {arp_request.pdst}")
dut_mac = arp_request.hwsrc
dut_ip = arp_request.psrc
assert arp_request.op == 1, "ARP type is not request!"
assert arp_request.hwsrc == "02:00:00:aa:bb:cc", "ARP hwsrc does not match expected"
assert arp_request.hwdst == "00:00:00:00:00:00", "ARP hwdst does not match expected"
assert arp_request.psrc == dut_ip, "ARP psrc does not match expected"
assert arp_request.pdst == tb_ip, "ARP pdst does not match expected"
arp_response = Ether(dst=dut_mac, src=tb_mac)
arp_response /= ARP(op="is-at", hwsrc=tb_mac, hwdst=dut_mac, psrc=tb_ip, pdst=dut_ip)
arp_response = arp_response.build()
await tb.mii_phy.rx.send(GmiiFrame.from_payload(arp_response))
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
tb.log.info(f"Packet Type: {packet.type:x}")
ip_packet = packet.payload
assert isinstance(ip_packet, IP)
tcp_packet = ip_packet.payload
assert isinstance(tcp_packet, TCP)
tb.log.info(f"Source Port: {tcp_packet.sport}")
tb.log.info(f"Dest Port: {tcp_packet.dport}")
tb.log.info(f"Seq: {tcp_packet.seq}")
tb.log.info(f"Ack: {tcp_packet.ack}")
tb.log.info(f"Data Offs: {tcp_packet.dataofs}")
tb.log.info(f"flags: {tcp_packet.flags}")
tb.log.info(f"window: {tcp_packet.window}")
tb.log.info(f"Checksum: {tcp_packet.chksum}")
t.send(ip_packet)
pkt = t.recv()
print(pkt)
tcp_synack = Ether(dst=dut_mac, src=tb_mac) / pkt
await tb.mii_phy.rx.send(GmiiFrame.from_payload(tcp_synack.build()))
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
tb.log.info(f"Packet Type: {packet.type:x}")
ip_packet = packet.payload
assert isinstance(ip_packet, IP)
tcp_packet = ip_packet.payload
assert isinstance(tcp_packet, TCP)
tb.log.info(f"Source Port: {tcp_packet.sport}")
tb.log.info(f"Dest Port: {tcp_packet.dport}")
tb.log.info(f"Seq: {tcp_packet.seq}")
tb.log.info(f"Ack: {tcp_packet.ack}")
tb.log.info(f"Data Offs: {tcp_packet.dataofs}")
tb.log.info(f"flags: {tcp_packet.flags}")
tb.log.info(f"window: {tcp_packet.window}")
tb.log.info(f"Checksum: {tcp_packet.chksum}")
t.send(ip_packet)
con, addr = serversocket.accept()
con.close()
serversocket.close()
while True:
pkt = t.recv()
if (pkt.proto == IP_PROTOS.tcp):
break
print(pkt)
tcp_fin = Ether(dst=dut_mac, src=tb_mac) / pkt
await tb.mii_phy.rx.send(GmiiFrame.from_payload(tcp_fin.build()))
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
tb.log.info(f"Packet Type: {packet.type:x}")
ip_packet = packet.payload
assert isinstance(ip_packet, IP)
tcp_packet = ip_packet.payload
assert isinstance(tcp_packet, TCP)
tb.log.info(f"Source Port: {tcp_packet.sport}")
tb.log.info(f"Dest Port: {tcp_packet.dport}")
tb.log.info(f"Seq: {tcp_packet.seq}")
tb.log.info(f"Ack: {tcp_packet.ack}")
tb.log.info(f"Data Offs: {tcp_packet.dataofs}")
tb.log.info(f"flags: {tcp_packet.flags}")
tb.log.info(f"window: {tcp_packet.window}")
tb.log.info(f"Checksum: {tcp_packet.chksum}")
t.send(ip_packet)
return
# Construct a descriptor in memry
tb.axil_ram.write_dword(0x00000000, 0x00001000)
tb.axil_ram.write_dword(0x00000004, 64)
tb.axil_ram.write_dword(0x00000008, 0)
tb.axil_ram.write_dword(0x0000000c, 0)
test_data = bytearray([x % 256 for x in range(256)])
tb.axil_ram.write(0x1000, test_data)
await tb.axil_master.write_dword(0x22c, 0)
await tb.axil_master.write_dword(0x220, 0x00000000)
await tb.axil_master.write_dword(0x224, 0x00000000)
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
t.send(packet.payload)
# con.recv(64)
serversocket.close()

139
hw/super6502_fpga/src/sub/network_processor/src/tcp_dest_decap.sv Normal file
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module tcp_dest_decap (
input i_clk,
input i_rst,
ip_intf.SLAVE s_ip,
ip_intf.MASTER m_ip,
output wire [15:0] o_tcp_dest,
output wire o_tcp_dest_valid
);
logic [15:0] tcp_dest, tcp_dest_next;
logic [31:0] pipe, pipe_next;
logic [3:0] pipe_valid, pipe_valid_next;
logic [3:0] pipe_last, pipe_last_next;
logic valid;
enum logic [1:0] {PORTS, PASSTHROUGH} state, state_next;
logic [1:0] counter, counter_next;
// We don't need the mac addresses or the ethertype.
assign m_ip.eth_src_mac = '0;
assign m_ip.eth_dest_mac = '0;
assign m_ip.eth_type = '0;
assign o_tcp_dest_valid = valid;
assign o_tcp_dest = tcp_dest;
skidbuffer #(
.DW(160)
) u_tcp_ip_hdr_skidbuffer (
.i_clk (i_clk),
.i_reset (i_rst),
.i_valid (s_ip.ip_hdr_valid),
.o_ready (s_ip.ip_hdr_ready),
.i_data ({
s_ip.ip_version,
s_ip.ip_ihl,
s_ip.ip_dscp,
s_ip.ip_ecn,
s_ip.ip_length,
s_ip.ip_identification,
s_ip.ip_flags,
s_ip.ip_fragment_offset,
s_ip.ip_ttl,
s_ip.ip_protocol,
s_ip.ip_header_checksum,
s_ip.ip_source_ip,
s_ip.ip_dest_ip
}),
.o_valid (m_ip.ip_hdr_valid),
.i_ready (m_ip.ip_hdr_ready),
.o_data ({
m_ip.ip_version,
m_ip.ip_ihl,
m_ip.ip_dscp,
m_ip.ip_ecn,
m_ip.ip_length,
m_ip.ip_identification,
m_ip.ip_flags,
m_ip.ip_fragment_offset,
m_ip.ip_ttl,
m_ip.ip_protocol,
m_ip.ip_header_checksum,
m_ip.ip_source_ip,
m_ip.ip_dest_ip
})
);
always_ff @(posedge i_clk) begin
if (i_rst) begin
tcp_dest <= '0;
pipe <= '0;
pipe_valid <= '0;
pipe_last <= '0;
state <= PORTS;
counter <= '0;
end else begin
tcp_dest <= tcp_dest_next;
pipe <= pipe_next;
pipe_valid <= pipe_valid_next;
pipe_last <= pipe_last_next;
state <= state_next;
counter <= counter_next;
end
end
always_comb begin
tcp_dest_next = tcp_dest;
state_next = state;
pipe_next = pipe;
pipe_valid_next = pipe_valid;
pipe_last_next = pipe_last;
counter_next = pipe;
s_ip.ip_payload_axis_tready = '0;
case (state)
PORTS: begin
s_ip.ip_payload_axis_tready = 1;
valid = '0;
if (s_ip.ip_payload_axis_tvalid) begin
counter_next = counter + 1;
pipe_valid_next = {pipe_valid[2:0], 1'b1};
pipe_next = {pipe_next[23:0], s_ip.ip_payload_axis_tdata};
if (counter == 2'h3) begin
state_next = PASSTHROUGH;
tcp_dest_next = pipe_next[15:0];
end
end
end
PASSTHROUGH: begin
// match ready except if we have seen last, then just finish it out.
pipe_valid_next = {pipe_valid[2:0], s_ip.ip_payload_axis_tvalid};
pipe_last_next = {pipe_last[2:0], s_ip.ip_payload_axis_tlast};
pipe_next = {pipe_next[23:0], s_ip.ip_payload_axis_tdata};
s_ip.ip_payload_axis_tready = m_ip.ip_payload_axis_tready;
m_ip.ip_payload_axis_tvalid = pipe_valid[3];
m_ip.ip_payload_axis_tlast = pipe_last[3];
m_ip.ip_payload_axis_tdata = pipe[31:24];
valid = '1;
if (pipe_last[3] && pipe_valid[3]) begin
state_next = PORTS;
end
end
endcase
end
endmodule

49
hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv Normal file
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@@ -0,0 +1,49 @@
import tcp_pkg::*;
module tcp_rx_ctrl (
input logic i_clk,
input logic i_rst,
output tcp_pkg::rx_msg_t o_rx_msg,
output logic o_rx_msg_valid,
input logic i_rx_msg_ack,
input logic [31:0] i_seq_number,
input logic [31:0] i_ack_number,
input logic [15:0] i_source_port,
input logic [15:0] i_dest_port,
input logic [7:0] i_flags,
input logic [15:0] i_window_size,
input logic i_hdr_valid,
output logic [31:0] o_ack_number
);
logic [31:0] ack_num, ack_num_next;
assign o_ack_number = ack_num;
always_ff @(posedge i_clk) begin
if (i_rst) begin
ack_num <= '0;
end else begin
ack_num <= ack_num_next;
end
end
always_comb begin
if (i_hdr_valid) begin
if (i_flags == 8'h12) begin
o_rx_msg = RX_MSG_RECV_SYNACK;
o_rx_msg_valid = '1;
ack_num_next = i_seq_number + 1;
end
if (i_flags == 8'h11) begin
o_rx_msg = RX_MSG_RECV_FIN;
o_rx_msg_valid = '1;
end
end
end
endmodule

100
hw/super6502_fpga/src/sub/network_processor/src/tcp_state_manager.sv Normal file
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@@ -0,0 +1,100 @@
import tcp_pkg::*;
module tcp_state_manager(
input wire i_clk,
input wire i_rst,
input wire i_enable,
input wire i_open,
output logic o_open_clr,
input wire i_close,
output logic o_close_clr,
output tcp_pkg::tx_ctrl_t o_tx_ctrl,
output logic o_tx_ctrl_valid,
input logic i_tx_ctrl_ack,
input tcp_pkg::rx_msg_t i_rx_msg,
input wire i_rx_msg_valid,
output logic o_rx_msg_ack
);
enum logic [3:0] {
IDLE,
SYN_RCVD, // In this design, this state should not be reached!
SYN_SENT_1,
SYN_SENT_2,
ESTABLISHED,
WAIT_CLOSE,
LAST_ACK,
TIME_WAIT,
FIN_WAIT_1,
FIN_WAIT_2
} tcp_state, tcp_state_next;
always_ff @(posedge i_clk) begin
if (i_rst) begin
tcp_state <= IDLE;
end else begin
if (~i_enable) begin
tcp_state <= IDLE;
end else begin
tcp_state <= tcp_state_next;
end
end
end
always_comb begin
tcp_state_next = tcp_state;
o_tx_ctrl_valid = '0;
o_tx_ctrl = TX_CTRL_NOP;
o_tx_ctrl_valid = '0;
o_rx_msg_ack = '0;
case (tcp_state)
IDLE: begin
if (i_open) begin
o_tx_ctrl = TX_CTRL_SEND_SYN;
o_tx_ctrl_valid = '1;
if (i_tx_ctrl_ack) begin
tcp_state_next = SYN_SENT_1;
end
end
end
SYN_SENT_1: begin
if (i_rx_msg_valid && i_rx_msg== RX_MSG_RECV_SYNACK) begin
tcp_state_next = SYN_SENT_2;
end
end
SYN_SENT_2: begin
o_tx_ctrl = TX_CTRL_SEND_ACK;
o_tx_ctrl_valid = '1;
if (i_tx_ctrl_ack) begin
tcp_state_next = ESTABLISHED;
end
end
ESTABLISHED: begin
if (i_rx_msg_valid && i_rx_msg == RX_MSG_RECV_FIN) begin
o_tx_ctrl = TX_CTRL_SEND_FIN;
o_tx_ctrl_valid = '1;
tcp_state_next = LAST_ACK;
end
end
LAST_ACK: begin
end
endcase
end
endmodule

131
hw/super6502_fpga/src/sub/network_processor/src/tcp_tx_ctrl.sv Normal file
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@@ -0,0 +1,131 @@
import tcp_pkg::*;
module tcp_tx_ctrl(
input i_clk,
input i_rst,
input tcp_pkg::tx_ctrl_t i_tx_ctrl,
input logic i_tx_ctrl_valid,
output logic o_tx_ctrl_ack,
output logic [15:0] o_ip_len,
output logic [31:0] o_seq_number,
output logic [31:0] o_ack_number,
output logic [7:0] o_flags,
output logic [15:0] o_window_size,
output logic o_hdr_valid,
axis_intf.SLAVE s_axis,
input logic [15:0] s_axis_len,
axis_intf.MASTER m_axis,
input wire i_packet_done
);
assign m_axis.tdata = s_axis.tdata;
assign m_axis.tkeep = s_axis.tkeep;
assign m_axis.tvalid = s_axis.tvalid;
assign s_axis.tready = m_axis.tready;
assign m_axis.tlast = s_axis.tlast;
assign m_axis.tid = s_axis.tid;
assign m_axis.tdest = s_axis.tdest;
assign m_axis.tuser = s_axis.tuser;
localparam FLAG_FIN = (1 << 0);
localparam FLAG_SYN = (1 << 1);
localparam FLAG_RST = (1 << 2);
localparam FLAG_PSH = (1 << 3);
localparam FLAG_ACK = (1 << 4);
localparam FLAG_URG = (1 << 5);
localparam FLAG_ECE = (1 << 6);
localparam FLAG_CWR = (1 << 7);
logic [31:0] seq_num, seq_num_next;
assign o_seq_number = seq_num;
enum logic [2:0] {IDLE, SEND_SYN, SEND_ACK, SEND_FIN, SEND_DATA} state, state_next;
always_ff @(posedge i_clk) begin
if (i_rst) begin
state <= IDLE;
seq_num <= '0;
end else begin
state <= state_next;
seq_num <= seq_num_next;
end
end
always_comb begin
state_next = state;
o_ack_number = '0;
o_flags = '0;
o_window_size = 16'b1;
o_hdr_valid = '0;
seq_num_next = seq_num;
o_ip_len = 16'd40; // default length of IP packet
case (state)
IDLE: begin
if (i_tx_ctrl_valid) begin
o_tx_ctrl_ack = '1;
case (i_tx_ctrl)
TX_CTRL_SEND_SYN: state_next = SEND_SYN;
TX_CTRL_SEND_ACK: state_next = SEND_ACK;
TX_CTRL_SEND_FIN: state_next = SEND_FIN;
endcase
end
if (s_axis.tvalid) begin
state_next = SEND_DATA;
end
end
SEND_SYN: begin
o_flags = FLAG_SYN;
o_hdr_valid = '1;
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num + 1;
end
end
SEND_ACK: begin
o_flags = FLAG_ACK;
o_hdr_valid = '1;
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num;
end
end
SEND_DATA: begin
o_flags = FLAG_ACK | FLAG_PSH;
o_ip_len = 16'd40 + s_axis_len; // default length of IP packet
o_hdr_valid = '1;
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num + s_axis_len;
end
end
SEND_FIN: begin
o_flags = FLAG_ACK | FLAG_FIN;
o_ip_len = 16'd40 + s_axis_len; // default length of IP packet
o_hdr_valid = '1;
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num + s_axis_len;
end
end
endcase
end
endmodule

15
init_env.sh
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@@ -4,16 +4,15 @@
# ENV=".env/$HOSTNAME"
export REPO_TOP=$(git rev-parse --show-toplevel)
export KICAD8_SYMBOL_DIR=$REPO_TOP/hw/kicad_library/symbols
export KICAD8_3DMODEL_DIR=$REPO_TOP/hw/kicad_library/3dmodels
export KICAD8_FOOTPRINT_DIR=$REPO_TOP/hw/kicad_library/footprints
export KICAD7_SYMBOL_DIR=$REPO_TOP/hw/kicad_library/symbols
export KICAD7_3DMODEL_DIR=$REPO_TOP/hw/kicad_library/3dmodels
export KICAD7_FOOTPRINT_DIR=$REPO_TOP/hw/kicad_library/footprints
#module load efinity/2023.1
module load verilator
module load gtkwave/3.3_gtk3
python3.12 -m venv .user_venv
. .user_venv/bin/activate
#module load efinity/2023.1
module load iverilog/12.0
module load gtkwave/3.3_gtk3
# pip install -r requirements.txt
pip install -r requirements.txt