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102-new-bo
| Author | SHA1 | Date | |
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21efb8ace8 |
1
.gitignore
vendored
1
.gitignore
vendored
@@ -8,6 +8,7 @@
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*.map
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*.map
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*.list
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*.list
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*.bin
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*.bin
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*.hex
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*.o
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*.o
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2
Makefile
2
Makefile
@@ -1,4 +1,4 @@
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ROM_TARGET=test_code/loop_test
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ROM_TARGET=bootloader
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INIT_HEX=hw/super6502_fpga/init_hex.mem
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INIT_HEX=hw/super6502_fpga/init_hex.mem
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HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin
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HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin
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@@ -23,7 +23,7 @@ all: waves
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waves: $(TB_NAME)
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waves: $(TB_NAME)
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# ./$(TB_NAME) -fst
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# ./$(TB_NAME) -fst
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./obj_dir/Vsim_top
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./obj_dir/Vsim_top | tee run.log
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$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(SD_IMAGE)
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$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(SD_IMAGE)
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# $(IVERILOG) -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
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# $(IVERILOG) -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
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@@ -197,8 +197,12 @@ initial begin
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button_resetn <= '0;
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button_resetn <= '0;
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repeat(10) @(clk_cpu);
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repeat(10) @(clk_cpu);
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button_resetn <= '1;
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button_resetn <= '1;
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repeat(20000) @(posedge clk_cpu);
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repeat(2000) @(posedge clk_cpu);
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$finish();
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$finish();
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end
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end
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always @(posedge w_cpu0_sync) begin
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$display("[%t] CPU Executed %x:%x", $time(), w_cpu0_addr, w_cpu0_data_from_dut);
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end
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endmodule
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endmodule
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19
sw/Makefile
Normal file
19
sw/Makefile
Normal file
@@ -0,0 +1,19 @@
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SD_IMAGE = sd_image.bin
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BOOTLOADER = bootloader/bootloader.bin
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all: $(SD_IMAGE) $(BOOTLOADER)
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$(BOOTLOADER):
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$(MAKE) -C bootloader bootloader.bin
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$(SD_IMAGE):
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dd if=/dev/zero of=$@ bs=1M count=256
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/sbin/mkfs.vfat $@
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udisksctl loop-setup --file $@
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udisksctl mount -b /dev/loop1
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udisksctl unmount -b /dev/loop1
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udisksctl loop-delete -b /dev/loop1
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clean:
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rm -rf $(SD_IMAGE)
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rm -rf $(BOOTLOADER)
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38
sw/bootloader/Makefile
Normal file
38
sw/bootloader/Makefile
Normal file
@@ -0,0 +1,38 @@
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CC=../toolchain/cc65/bin/cl65
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LD=../toolchain/cc65/bin/cl65
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CFLAGS=-T -t none -I. --cpu "65C02"
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LDFLAGS=-C link.ld -m $(NAME).map
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NAME=bootloader
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BIN=$(NAME).bin
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HEX=$(NAME).hex
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LISTS=lists
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SRCS=$(wildcard *.s) $(wildcard *.c)
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SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
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OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
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OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
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all: $(HEX)
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$(HEX): $(BIN)
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objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
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$(BIN): $(OBJS)
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$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
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%.o: %.c $(LISTS)
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$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
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%.o: %.s $(LISTS)
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$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
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$(LISTS):
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mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
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.PHONY: clean
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clean:
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rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
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25
sw/bootloader/bootloader.s
Normal file
25
sw/bootloader/bootloader.s
Normal file
@@ -0,0 +1,25 @@
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.export _init, _nmi_int, _irq_int
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.segment "VECTORS"
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.addr _nmi_int ; NMI vector
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.addr _init ; Reset vector
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.addr _irq_int ; IRQ/BRK vector
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SDRAM= $200
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.code
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_nmi_int:
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_irq_int:
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_init:
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lda #$00
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@start:
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sta SDRAM
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cmp SDRAM
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bne @end
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ina
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bra @start
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@end: bra @end
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30
sw/bootloader/link.ld
Normal file
30
sw/bootloader/link.ld
Normal file
@@ -0,0 +1,30 @@
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MEMORY
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{
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RAM: start = $0000, size = $200;
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ROM: start = $F000, size = $1000, file = %O;
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}
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SEGMENTS {
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ZEROPAGE: load = RAM, type = zp, define = yes;
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DATA: load = ROM, type = rw, define = yes;
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CODE: load = ROM, type = ro;
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RODATA: load = ROM, type = ro;
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VECTORS: load = ROM, type = ro, start = $FFFA;
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}
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FEATURES {
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CONDES: segment = STARTUP,
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type = constructor,
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label = __CONSTRUCTOR_TABLE__,
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count = __CONSTRUCTOR_COUNT__;
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CONDES: segment = STARTUP,
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type = destructor,
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label = __DESTRUCTOR_TABLE__,
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count = __DESTRUCTOR_COUNT__;
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}
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SYMBOLS {
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# Define the stack size for the application
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__STACKSIZE__: value = $0200, type = weak;
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__STACKSTART__: type = weak, value = $0800; # 2k stack
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}
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39
sw/kernel/Makefile
Normal file
39
sw/kernel/Makefile
Normal file
@@ -0,0 +1,39 @@
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CC=../toolchain/cc65/bin/cl65
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LD=../toolchain/cc65/bin/cl65
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CFLAGS=-T -t none -I. --cpu "65C02"
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LDFLAGS=-C link.ld -m $(NAME).map
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NAME=bootloader
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BIN=$(NAME).bin
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HEX=$(NAME).hex
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LISTS=lists
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SRCS=$(wildcard *.s) $(wildcard *.c)
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SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
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OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
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OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
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# Make sure the kernel linked to correct address, no relocation!
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all: $(HEX)
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$(HEX): $(BIN)
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objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
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$(BIN): $(OBJS)
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$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
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%.o: %.c $(LISTS)
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$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
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%.o: %.s $(LISTS)
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$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
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$(LISTS):
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mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
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.PHONY: clean
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clean:
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rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
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9
sw/kernel/kernel.s
Normal file
9
sw/kernel/kernel.s
Normal file
@@ -0,0 +1,9 @@
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.segment "ENTRY"
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.addr main
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.code
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main:
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bra main
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30
sw/kernel/link.ld
Normal file
30
sw/kernel/link.ld
Normal file
@@ -0,0 +1,30 @@
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MEMORY
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{
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RAM: start = $0000, size = $200;
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KERNEL: start = $8000, size = $7000, file = %O;
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}
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SEGMENTS {
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ZEROPAGE: load = RAM, type = zp, define = yes;
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ENTRY: load = KERNEL, type = ro, start = $8000;
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DATA: load = KERNEL, type = rw, define = yes;
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CODE: load = KERNEL, type = ro;
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RODATA: load = KERNEL, type = ro;
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}
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FEATURES {
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CONDES: segment = STARTUP,
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type = constructor,
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label = __CONSTRUCTOR_TABLE__,
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count = __CONSTRUCTOR_COUNT__;
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CONDES: segment = STARTUP,
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type = destructor,
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label = __DESTRUCTOR_TABLE__,
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count = __DESTRUCTOR_COUNT__;
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}
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SYMBOLS {
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# Define the stack size for the application
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__STACKSIZE__: value = $0200, type = weak;
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__STACKSTART__: type = weak, value = $0800; # 2k stack
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}
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Reference in New Issue
Block a user