fileset source file ../source/axi4_sdram_controller.v is_present

fileset source file ../source/dual_clock_fifo_wrapper.v is_present

fileset source file ../source/sdram_simple_dual_port_ram.v is_present

fileset example file ../source_exp/axi4_sdram_controller_test.v is_present

fileset example file ../fpga/T20F256_devkit/axi4/axi4_sdram_controller_test.peri.xml is_present

fileset example file ../fpga/T20F256_devkit/axi4/axi4_sdram_controller.xml is_present

fileset example file ../fpga/T20F256_devkit/axi4/debug_profile.json is_present

fileset example file ../fpga/constraints/axi4_sdram_controller_test.sdc is_present

fileset example file ../source_exp/native_debug_top.v is_present

fileset example file ../source_exp/native_sdram_controller_test.v is_present

fileset example file ../fpga/T20F256_devkit/native/debug_profile.json is_present

fileset example file ../fpga/T20F256_devkit/native/sdram_controller_test.peri.xml is_present

fileset example file ../fpga/T20F256_devkit/native/sdram_controller.xml is_present

fileset example file ../fpga/constraints/sdram_controller_native_test.sdc is_present

fileset testbench file ../testbench/native_sdram_controller_tb.v is_present

fileset testbench file ../testbench/axi4_sdram_controller_tb.v is_present

fileset testbench file ../source_exp/axi4_debug_top.v is_present

fileset testbench file ../source_exp/axi4_sdram_controller_test.v is_present

fileset testbench file ../source_exp/native_debug_top.v is_present

fileset testbench file ../source_exp/native_sdram_controller_test.v is_present

fileset testbench file ../testbench/native/modelsim.do is_present