# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:36:56  March 05, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		super6502_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY super6502
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:36:56  MARCH 05, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_V10 -to cpu_led
set_location_assignment PIN_W10 -to cpu_vpb
set_location_assignment PIN_V9 -to cpu_resb
set_location_assignment PIN_W9 -to cpu_rdy
set_location_assignment PIN_V8 -to cpu_sob
set_location_assignment PIN_V7 -to cpu_phi2
set_location_assignment PIN_W6 -to cpu_be
set_location_assignment PIN_W5 -to cpu_rwb
set_location_assignment PIN_AA14 -to cpu_data[0]
set_location_assignment PIN_W12 -to cpu_data[1]
set_location_assignment PIN_AB12 -to cpu_data[2]
set_location_assignment PIN_AB11 -to cpu_data[3]
set_location_assignment PIN_AB10 -to cpu_data[4]
set_location_assignment PIN_AA9 -to cpu_data[5]
set_location_assignment PIN_AA8 -to cpu_data[6]
set_location_assignment PIN_AA7 -to cpu_data[7]
set_location_assignment PIN_AA6 -to cpu_addr[15]
set_location_assignment PIN_AA5 -to cpu_addr[14]
set_location_assignment PIN_AB3 -to cpu_addr[13]
set_location_assignment PIN_AB2 -to cpu_addr[12]
set_location_assignment PIN_AA2 -to cpu_addr[11]
set_location_assignment PIN_Y3 -to cpu_addr[10]
set_location_assignment PIN_Y4 -to cpu_addr[9]
set_location_assignment PIN_Y5 -to cpu_addr[8]
set_location_assignment PIN_Y6 -to cpu_addr[7]
set_location_assignment PIN_Y7 -to cpu_addr[6]
set_location_assignment PIN_Y8 -to cpu_addr[5]
set_location_assignment PIN_AA10 -to cpu_addr[4]
set_location_assignment PIN_W11 -to cpu_addr[3]
set_location_assignment PIN_Y11 -to cpu_addr[2]
set_location_assignment PIN_AB13 -to cpu_addr[1]
set_location_assignment PIN_W13 -to cpu_addr[0]
set_location_assignment PIN_AA15 -to cpu_sync
set_location_assignment PIN_V5 -to cpu_nmib
set_location_assignment PIN_W7 -to cpu_mlb
set_location_assignment PIN_W8 -to cpu_irqb
set_location_assignment PIN_P11 -to clk
set_location_assignment PIN_B8 -to rst
set_global_assignment -name QIP_FILE ram.qip
set_global_assignment -name SDC_FILE super6502.sdc
set_global_assignment -name QIP_FILE rom.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top