"/home/byron/Software/efinity/2021.2/bin/efx_map" --project "super6502" --root "super6502" --write-efx-verilog "/home/byron/Projects/super6502/hw/efinix_fpga/outflow/super6502.map.v" --write-premap-module "/home/byron/Projects/super6502/hw/efinix_fpga/outflow/super6502.elab.vdb" --binary-db "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.vdb" --device "T20F256" --family "Trion" --mode "speed" --max_ram "-1" --max_mult "-1" --infer-clk-enable "3" --infer-sync-set-reset "1" --fanout-limit "0" --bram_output_regs_packing "1" --retiming "1" --seq_opt "1" --blast_const_operand_adders "1" --operator-sharing "0" --optimize-adder-tree "0" --mult_input_regs_packing "1" --mult_output_regs_packing "1" --veri_option "verilog_mode=sv_09,vhdl_mode=vhdl_2008" --work-dir "/home/byron/Projects/super6502/hw/efinix_fpga/work_syn" --output-dir "/home/byron/Projects/super6502/hw/efinix_fpga/outflow" --project-xml "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml" --I "/home/byron/Projects/super6502/hw/efinix_fpga" --I "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram"