[submodule "hw/super6502_fpga/src/sub/rtl-common"]
	path = hw/super6502_fpga/src/sub/rtl-common
	url = ../rtl-common.git
[submodule "sw/toolchain/cc65"]
	path = sw/toolchain/cc65
	url = ../cc65.git
[submodule "hw/super6502_fpga/src/sim/sub/verilog-6502"]
	path = hw/super6502_fpga/src/sim/sub/verilog-6502
	url = ../verilog-6502.git
[submodule "hw/super6502_fpga/src/sub/wb2axip"]
	path = hw/super6502_fpga/src/sub/wb2axip
	url = ../wb2axip.git
[submodule "hw/super6502_fpga/src/sub/sdspi"]
	path = hw/super6502_fpga/src/sub/sd_controller_wrapper/sdspi
	url = ../sdspi.git
[submodule "hw/super6502_fpga/src/sub/verilog-ethernet"]
	path = hw/super6502_fpga/src/sub/verilog-ethernet
	url = ../verilog-ethernet.git
[submodule "hw/super6502_fpga/src/sub/stream_dmas"]
	path = hw/super6502_fpga/src/sub/stream_dmas
	url = ../stream_dmas.git
[submodule "hw/super6502_fpga/src/sub/interfaces"]
	path = hw/super6502_fpga/src/sub/interfaces
	url = ../interfaces.git
[submodule "hw/super6502_fpga/src/sub/my-fifos"]
	path = hw/super6502_fpga/src/sub/my-fifos
	url = ../my-fifos.git