{
    "args": [
        "-o",
        "sdram",
        "--base_path",
        "/home/byron/Projects/super6502/hw/efinix_fpga/ip",
        "--vlnv",
        {
            "vendor": "efinixinc.com",
            "library": "memory_controller",
            "name": "efx_sdram_controller",
            "version": "1.5"
        }
    ],
    "conf": {
        "fCK_MHz": "200",
        "tIORT_u": "2",
        "CL": "3",
        "DDIO_TYPE": "0",
        "DQ_GROUP": "2",
        "ROW_WIDTH": "13",
        "COL_WIDTH": "9",
        "tPWRUP": "200000",
        "tRAS": "44",
        "tRAS_MAX": "120000",
        "tRC": "66",
        "tRCD": "20",
        "tREF": "64000000",
        "tRFC ": "66",
        "tRP": "20",
        "SDRAM_MODE": "0",
        "DATA_RATE": "2"
    },
    "output": {
        "external_source": [
            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v",
            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_define.vh",
            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_tmpl.vhd",
            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_tmpl.v"
        ]
    },
    "sw_version": "2021.2.323",
    "generated_date": "2022-06-12T00:16:17.036312"
}