///////////////////////////////////
// Efinity Synthesis Started 
// Jun 09, 2022 21:36:12
///////////////////////////////////


///////////////////////////////////
// Efinity Synthesis Started 
// Jun 09, 2022 21:36:40
///////////////////////////////////


///////////////////////////////////
// Efinity Synthesis Started 
// Jun 09, 2022 21:42:28
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)

///////////////////////////////////
// Efinity Synthesis Started 
// Jun 11, 2022 12:05:39
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)

///////////////////////////////////
// Efinity Synthesis Started 
// Jun 11, 2022 19:19:40
///////////////////////////////////


///////////////////////////////////
// Efinity Synthesis Started 
// Jun 11, 2022 19:20:04
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)

///////////////////////////////////
// Efinity Synthesis Started 
// Jun 11, 2022 19:20:55
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)

///////////////////////////////////
// Efinity Synthesis Started 
// Jun 11, 2022 19:21:29
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)

///////////////////////////////////
// Efinity Synthesis Started 
// Jun 11, 2022 19:21:33
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)

///////////////////////////////////
// Efinity Synthesis Started 
// Jun 13, 2022 19:05:46
///////////////////////////////////


///////////////////////////////////
// Efinity Synthesis Started 
// Jun 13, 2022 19:08:09
///////////////////////////////////


///////////////////////////////////
// Efinity Synthesis Started 
// Jun 13, 2022 19:08:21
///////////////////////////////////

[EFX-0011 VERI-WARNING] port 'i_sysclk' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'o_pll_reset' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)