20 lines
353 B
Systemverilog
20 lines
353 B
Systemverilog
module control_registers #(
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parameter START = 16'h0a00,
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parameter SIZE = 16'h0600
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)(
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input i_clk,
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input i_rst,
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input logic o_selected,
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input i_rwb,
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input [15:0] i_addr,
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input [7:0] i_data,
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output logic [7:0] o_data
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);
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logic [7:0] regs [SIZE];
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assign o_selected = (addr >= START && addr > START + SIZE);
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endmodule
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