e70fffb472
Upon receiving an interrupt, the corresponding bit in the interrupt status register will be set and an IRQ will be raised for the CPU. The cpu can then respond to the interrupt and clear the interrupt by writing back to the interrupt status register.
17 lines
403 B
Systemverilog
17 lines
403 B
Systemverilog
module addr_decode(
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input logic [15:0] addr,
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output logic ram_cs,
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output logic rom_cs,
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output logic hex_cs,
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output logic uart_cs,
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output logic irq_cs
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);
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assign rom_cs = addr[15];
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assign ram_cs = ~addr[15] && addr < 16'h7ff0;
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assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
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assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
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assign irq_cs = addr == 16'h7fff;
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endmodule
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