e70fffb472
Upon receiving an interrupt, the corresponding bit in the interrupt status register will be set and an IRQ will be raised for the CPU. The cpu can then respond to the interrupt and clear the interrupt by writing back to the interrupt status register.
76 lines
1.3 KiB
Systemverilog
76 lines
1.3 KiB
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk_50, rst_n, button_1;
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logic [15:0] cpu_addr;
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wire [7:0] cpu_data;
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logic [7:0] cpu_data_in;
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logic [7:0] cpu_data_out;
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logic cpu_vpb, cpu_mlb, cpu_rwb, cpu_sync;
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logic cpu_led, cpu_resb, cpu_rdy, cpu_sob, cpu_irqb;
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logic cpu_phi2, cpu_be, cpu_nmib;
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logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
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logic UART_RXD, UART_TXD;
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assign cpu_data = ~cpu_rwb ? cpu_data_out : 'z;
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assign cpu_data_in = cpu_data;
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super6502 dut(.*);
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always #1 clk_50 = clk_50 === 1'b0;
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always #100 dut.clk = dut.clk === 1'b0;
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always @(posedge dut.clk) begin
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dut.cpu_phi2 <= ~dut.cpu_phi2;
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end
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logic [7:0] _tmp_data;
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initial begin
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rst_n <= '0;
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cpu_addr <= 16'h7fff;
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cpu_rwb <= '1;
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button_1 <= '1;
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repeat(10) @(posedge dut.clk);
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rst_n <= '1;
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repeat(10) @(posedge dut.clk);
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button_1 <= '0;
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@(posedge dut.clk);
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button_1 <= '1;
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@(posedge dut.clk);
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assert(cpu_data[0] == '1)
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else begin
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$error("IRQ location should have bit 1 set!");
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end
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@(posedge dut.clk);
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_tmp_data <= cpu_data_in;
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@(posedge dut.clk);
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_tmp_data <= _tmp_data & ~8'b1;
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@(posedge dut.clk);
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cpu_data_out <= _tmp_data;
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cpu_rwb <= '0;
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@(posedge dut.clk);
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cpu_rwb <= '1;
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repeat (5) @(posedge dut.clk);
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$finish();
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end
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endmodule
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