257 lines
7.2 KiB
Systemverilog
257 lines
7.2 KiB
Systemverilog
module super6502_fpga(
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input logic i_sysclk, // Controller Clock (100MHz)
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input logic i_sdrclk, // t_su and t_wd clock (200MHz)
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input logic i_tACclk, // t_ac clock (200MHz)
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input clk_cpu,
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input button_reset,
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input pll_cpu_locked,
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output logic pll_cpu_reset,
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input i_pll_locked,
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output logic o_pll_reset,
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input [7:0] i_cpu0_data_from_cpu,
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input i_cpu0_sync,
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input i_cpu0_rwb,
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input logic [15:0] i_cpu0_addr,
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output logic [7:0] o_cpu0_data_from_dut,
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output logic [7:0] o_cpu0_data_oe,
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output logic o_cpu0_irqb,
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output logic o_cpu0_nmib,
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output logic o_cpu0_rdy,
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output logic o_cpu0_reset,
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output logic o_clk_phi2
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);
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localparam ADDR_WIDTH = 32;
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localparam DATA_WIDTH = 32;
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assign pll_cpu_reset = '1;
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assign o_pll_reset = '1;
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assign o_cpu0_nmib = '1;
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assign o_clk_phi2 = clk_cpu;
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assign o_cpu0_data_oe = {8{i_cpu0_rwb}};
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logic master_reset;
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assign master_reset = button_reset;
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logic cpu0_AWVALID;
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logic cpu0_AWREADY;
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logic [ADDR_WIDTH-1:0] cpu0_AWADDR;
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logic cpu0_WVALID;
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logic cpu0_WREADY;
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logic [DATA_WIDTH-1:0] cpu0_WDATA;
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logic [DATA_WIDTH/8-1:0] cpu0_WSTRB;
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logic cpu0_BVALID;
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logic cpu0_BREADY;
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logic [1:0] cpu0_BRESP;
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logic cpu0_ARVALID;
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logic cpu0_ARREADY;
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logic [ADDR_WIDTH-1:0] cpu0_ARADDR;
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logic cpu0_RVALID;
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logic cpu0_RREADY;
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logic [DATA_WIDTH-1:0] cpu0_RDATA;
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logic [1:0] cpu0_RRESP;
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logic ram_awvalid;
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logic ram_awready;
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logic [ADDR_WIDTH-1:0] ram_awaddr;
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logic ram_wvalid;
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logic ram_wready;
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logic [DATA_WIDTH-1:0] ram_wdata;
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logic [DATA_WIDTH/8-1:0] ram_wstrb;
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logic ram_bvalid;
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logic ram_bready;
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logic [1:0] ram_bresp;
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logic ram_arvalid;
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logic ram_arready;
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logic [ADDR_WIDTH-1:0] ram_araddr;
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logic ram_rvalid;
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logic ram_rready;
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logic [DATA_WIDTH-1:0] ram_rdata;
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logic [1:0] ram_rresp;
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logic rom_awvalid;
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logic rom_awready;
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logic [ADDR_WIDTH-1:0] rom_awaddr;
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logic rom_wvalid;
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logic rom_wready;
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logic [DATA_WIDTH-1:0] rom_wdata;
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logic [DATA_WIDTH/8-1:0] rom_wstrb;
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logic rom_bvalid;
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logic rom_bready;
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logic [1:0] rom_bresp;
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logic rom_arvalid;
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logic rom_arready;
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logic [ADDR_WIDTH-1:0] rom_araddr;
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logic rom_rvalid;
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logic rom_rready;
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logic [DATA_WIDTH-1:0] rom_rdata;
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logic [1:0] rom_rresp;
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cpu_wrapper u_cpu_wrapper_0(
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.i_clk_cpu (clk_cpu),
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.i_clk_100 (i_sysclk),
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.i_rst (~master_reset),
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.o_cpu_rst (o_cpu0_reset),
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.o_cpu_rdy (o_cpu0_rdy),
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.o_cpu_be (),
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.o_cpu_irqb (o_cpu0_irqb),
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.o_cpu_nmib (),
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.o_cpu_sob (),
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.i_cpu_rwb (i_cpu0_rwb),
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.i_cpu_sync (i_cpu0_sync),
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.i_cpu_vpb ('0),
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.i_cpu_mlb ('0),
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.i_cpu_addr (i_cpu0_addr),
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.i_cpu_data (i_cpu0_data_from_cpu),
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.o_cpu_data (o_cpu0_data_from_dut),
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.o_AWVALID (cpu0_AWVALID),
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.i_AWREADY (cpu0_AWREADY),
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.o_AWADDR (cpu0_AWADDR),
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.o_WVALID (cpu0_WVALID),
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.i_WREADY (cpu0_WREADY),
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.o_WDATA (cpu0_WDATA),
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.o_WSTRB (cpu0_WSTRB),
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.i_BVALID (cpu0_BVALID),
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.o_BREADY (cpu0_BREADY),
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.i_BRESP (cpu0_BRESP),
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.o_ARVALID (cpu0_ARVALID),
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.i_ARREADY (cpu0_ARREADY),
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.o_ARADDR (cpu0_ARADDR),
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.i_RVALID (cpu0_RVALID),
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.o_RREADY (cpu0_RREADY),
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.i_RDATA (cpu0_RDATA),
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.i_RRESP (cpu0_RRESP),
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.i_irq('0),
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.i_nmi('0)
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);
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axi_crossbar #(
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.N_INITIATORS(1),
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.N_TARGETS(2)
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) u_crossbar (
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.clk(i_sysclk),
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.rst(~master_reset),
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.ini_araddr ({cpu0_ARADDR }),
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.ini_arvalid ({cpu0_ARVALID }),
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.ini_arready ({cpu0_ARREADY }),
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.ini_rdata ({cpu0_RDATA }),
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.ini_rresp ({cpu0_RRESP }),
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.ini_rvalid ({cpu0_RVALID }),
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.ini_rready ({cpu0_RREADY }),
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.ini_awaddr ({cpu0_AWADDR }),
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.ini_awready ({cpu0_AWREADY }),
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.ini_awvalid ({cpu0_AWVALID }),
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.ini_wvalid ({cpu0_WVALID }),
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.ini_wready ({cpu0_WREADY }),
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.ini_wdata ({cpu0_WDATA }),
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.ini_wstrb ({cpu0_WSTRB }),
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.ini_bresp ({cpu0_BRESP }),
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.ini_bvalid ({cpu0_BVALID }),
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.ini_bready ({cpu0_BREADY }),
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.tgt_araddr ({ram_araddr, rom_araddr }),
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.tgt_arvalid ({ram_arvalid, rom_arvalid }),
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.tgt_arready ({ram_arready, rom_arready }),
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.tgt_rdata ({ram_rdata, rom_rdata }),
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.tgt_rresp ({ram_rresp, rom_rresp }),
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.tgt_rvalid ({ram_rvalid, rom_rvalid }),
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.tgt_rready ({ram_rready, rom_rready }),
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.tgt_awaddr ({ram_awaddr, rom_awaddr }),
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.tgt_awvalid ({ram_awvalid, rom_awvalid }),
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.tgt_awready ({ram_awready, rom_awready }),
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.tgt_wdata ({ram_wdata, rom_wdata }),
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.tgt_wvalid ({ram_wvalid, rom_wvalid }),
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.tgt_wready ({ram_wready, rom_wready }),
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.tgt_wstrb ({ram_wstrb, rom_wstrb }),
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.tgt_bresp ({ram_bresp, rom_bresp }),
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.tgt_bvalid ({ram_bvalid, rom_bvalid }),
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.tgt_bready ({ram_bready, rom_bready })
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);
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axi4_lite_rom #(
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.ROM_SIZE(8),
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.ROM_INIT_FILE("init_hex.mem")
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) u_rom (
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.i_clk(i_sysclk),
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.i_rst(~master_reset),
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.o_AWREADY(rom_awready),
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.o_WREADY(rom_wready),
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.o_BVALID(rom_bvalid),
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.i_BREADY(rom_bready),
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.o_BRESP(rom_bresp),
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.i_ARVALID(rom_arvalid),
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.o_ARREADY(rom_arready),
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.i_ARADDR(rom_araddr),
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.i_ARPROT('0),
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.o_RVALID(rom_rvalid),
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.i_RREADY(rom_rready),
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.o_RDATA(rom_rdata),
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.o_RRESP(rom_rresp),
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.i_AWVALID(rom_awvalid),
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.i_AWADDR(rom_awaddr),
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.i_AWPROT('0),
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.i_WVALID(rom_wvalid),
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.i_WDATA(rom_wdata),
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.i_WSTRB(rom_wstrb)
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);
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axi4_lite_ram #(
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.RAM_SIZE(9)
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) u_ram(
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.i_clk(i_sysclk),
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.i_rst(~master_reset),
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.o_AWREADY(ram_awready),
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.o_WREADY(ram_wready),
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.o_BVALID(ram_bvalid),
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.i_BREADY(ram_bready),
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.o_BRESP(ram_bresp),
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.i_ARVALID(ram_arvalid),
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.o_ARREADY(ram_arready),
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.i_ARADDR(ram_araddr),
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.i_ARPROT('0),
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.o_RVALID(ram_rvalid),
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.i_RREADY(ram_rready),
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.o_RDATA(ram_rdata),
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.o_RRESP(ram_rresp),
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.i_AWVALID(ram_awvalid),
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.i_AWADDR(ram_awaddr),
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.i_AWPROT('0),
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.i_WVALID(ram_wvalid),
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.i_WDATA(ram_wdata),
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.i_WSTRB(ram_wstrb)
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);
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endmodule |