1128b986eb
The SD card expects data to transition on falling edges and be stable on rising edges. Additionally, writes from the CPU were not handled with correct timing. Now, there is an extra state when writing to the command register so that the command is properly latched before the CRC is calculated.
136 lines
2.7 KiB
Systemverilog
136 lines
2.7 KiB
Systemverilog
module sd_controller(
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input clk,
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input sd_clk,
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input rst,
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input [2:0] addr,
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input [7:0] data,
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input cs,
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input rw,
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input i_sd_cmd,
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output logic o_sd_cmd,
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input i_sd_data,
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output logic o_sd_data
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);
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logic [31:0] arg;
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logic [5:0] cmd;
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logic [47:0] rxcmd_buf;
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typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD} macro_t;
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struct packed {
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macro_t macro;
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logic [5:0] count;
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} state, next_state;
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always_ff @(posedge clk) begin
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if (rst) begin
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state.macro <= IDLE;
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state.count <= '0;
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end else begin
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if (state.macro == TXCMD || state.macro == CRC) begin
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if (sd_clk) begin
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state <= next_state;
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end
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end else begin
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state <= next_state;
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end
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end
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if (cs & ~rw) begin
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if (addr < 4'h4) begin
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arg[8 * addr +: 8] <= data;
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end else if (addr == 4'h4) begin
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cmd <= data;
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end
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end
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if (state.macro == RXCMD) begin
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rxcmd_buf[6'd46-state.count] <= i_sd_cmd; //we probabily missed bit 47
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end
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end
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logic [6:0] crc;
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logic load_crc;
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logic crc_valid;
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logic [39:0] _packet;
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assign _packet = {1'b0, 1'b1, cmd, arg};
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logic [47:0] packet_crc;
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assign packet_crc = {_packet, crc, 1'b1};
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crc7 u_crc7(
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.clk(clk),
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.rst(rst),
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.load(load_crc),
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.data_in(_packet),
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.crc_out(crc),
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.valid(crc_valid)
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);
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always_comb begin
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next_state = state;
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case (state.macro)
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IDLE: begin
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if (~i_sd_cmd) begin // receive data if sd pulls cmd low
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next_state.macro = RXCMD;
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end
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if (addr == 4'h4 & cs & ~rw) begin // transmit if cpu writes to cmd
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next_state.macro = LOAD;
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end
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end
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LOAD: begin
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next_state.macro = CRC;
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end
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CRC: begin
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next_state.macro = TXCMD;
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end
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TXCMD: begin
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if (state.count < 47) begin
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next_state.count = state.count + 6'b1;
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end else begin
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next_state.macro = IDLE;
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next_state.count = '0;
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end
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end
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RXCMD: begin
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if (state.count < 47) begin
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next_state.count = state.count + 6'b1;
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end else begin
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next_state.macro = IDLE;
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next_state.count = '0;
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end
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end
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endcase
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end
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always_comb begin
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o_sd_cmd = '1; //default to 1
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o_sd_data = '1;
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load_crc = '0;
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case (state.macro)
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IDLE:;
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CRC: begin
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load_crc = '1;
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end
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TXCMD: begin
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o_sd_cmd = packet_crc[6'd47 - state.count];
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end
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RXCMD:;
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endcase
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end
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endmodule
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