42ad901ba4
Add 16x16 multiplier. Pretty simple. Address 0-1 is multipled by address 2-3 and the result is in address 4-7, all little endian of course.
46 lines
738 B
Systemverilog
46 lines
738 B
Systemverilog
module multiplier(
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input clk,
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input reset,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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input [2:0] addr
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);
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logic [15:0] a, b;
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logic [31:0] out;
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always_ff @(negedge clk) begin
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if (reset) begin
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a <= '0;
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b <= '0;
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end
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if (cs & ~rwb) begin
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case (addr)
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3'h0: begin
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a[7:0] <= i_data;
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end
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3'h1: begin
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a[15:8] <= i_data;
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end
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3'h2: begin
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b[7:0] <= i_data;
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end
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3'h3: begin
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b[15:8] <= i_data;
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end
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endcase
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end
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end
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assign out = a * b;
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assign o_data = out[((addr-4)*8)+:8];
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endmodule |