510 lines
17 KiB
JSON
510 lines
17 KiB
JSON
{
|
|
"debug_cores": [
|
|
{
|
|
"name": "la0",
|
|
"type": "la",
|
|
"uuid": "2d64f403f73d428c8b583d71d6829ed4",
|
|
"trigin_en": false,
|
|
"trigout_en": false,
|
|
"auto_inserted": true,
|
|
"capture_control": false,
|
|
"data_depth": 8192,
|
|
"input_pipeline": 1,
|
|
"probes": [
|
|
{
|
|
"name": "cpu_data_in",
|
|
"width": 8,
|
|
"probe_type": 1
|
|
},
|
|
{
|
|
"name": "cpu_rwb",
|
|
"width": 1,
|
|
"probe_type": 1
|
|
},
|
|
{
|
|
"name": "cpu_addr",
|
|
"width": 16,
|
|
"probe_type": 1
|
|
},
|
|
{
|
|
"name": "cpu_sync",
|
|
"width": 1,
|
|
"probe_type": 1
|
|
},
|
|
{
|
|
"name": "cpu_rdy",
|
|
"width": 1,
|
|
"probe_type": 1
|
|
},
|
|
{
|
|
"name": "w_sdram_addr",
|
|
"width": 25,
|
|
"probe_type": 1
|
|
}
|
|
]
|
|
}
|
|
],
|
|
"connections": [
|
|
{
|
|
"command": "add_ports",
|
|
"id": 1,
|
|
"args": {
|
|
"netlist": "super6502",
|
|
"ports": [
|
|
{
|
|
"name": "jtag_inst1_CAPTURE",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_DRCK",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_RESET",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_RUNTEST",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_SEL",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_SHIFT",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_TCK",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_TDI",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_TMS",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_UPDATE",
|
|
"dir": "in",
|
|
"width": 1
|
|
},
|
|
{
|
|
"name": "jtag_inst1_TDO",
|
|
"dir": "out",
|
|
"width": 1
|
|
}
|
|
]
|
|
}
|
|
},
|
|
{
|
|
"command": "instantiate",
|
|
"netlist": "edb_top",
|
|
"id": 2,
|
|
"instance": "edb_top_inst"
|
|
},
|
|
{
|
|
"command": "connect",
|
|
"id": 3,
|
|
"args": {
|
|
"instance": "edb_top_inst",
|
|
"ports": [
|
|
{
|
|
"name": "bscan_CAPTURE",
|
|
"net": "jtag_inst1_CAPTURE"
|
|
},
|
|
{
|
|
"name": "bscan_DRCK",
|
|
"net": "jtag_inst1_DRCK"
|
|
},
|
|
{
|
|
"name": "bscan_RESET",
|
|
"net": "jtag_inst1_RESET"
|
|
},
|
|
{
|
|
"name": "bscan_RUNTEST",
|
|
"net": "jtag_inst1_RUNTEST"
|
|
},
|
|
{
|
|
"name": "bscan_SEL",
|
|
"net": "jtag_inst1_SEL"
|
|
},
|
|
{
|
|
"name": "bscan_SHIFT",
|
|
"net": "jtag_inst1_SHIFT"
|
|
},
|
|
{
|
|
"name": "bscan_TCK",
|
|
"net": "jtag_inst1_TCK"
|
|
},
|
|
{
|
|
"name": "bscan_TDI",
|
|
"net": "jtag_inst1_TDI"
|
|
},
|
|
{
|
|
"name": "bscan_TMS",
|
|
"net": "jtag_inst1_TMS"
|
|
},
|
|
{
|
|
"name": "bscan_UPDATE",
|
|
"net": "jtag_inst1_UPDATE"
|
|
},
|
|
{
|
|
"name": "bscan_TDO",
|
|
"net": "jtag_inst1_TDO"
|
|
},
|
|
{
|
|
"name": "la0_clk",
|
|
"net": "clk_2",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[0]",
|
|
"net": "cpu_data_in[0]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[1]",
|
|
"net": "cpu_data_in[1]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[2]",
|
|
"net": "cpu_data_in[2]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[3]",
|
|
"net": "cpu_data_in[3]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[4]",
|
|
"net": "cpu_data_in[4]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[5]",
|
|
"net": "cpu_data_in[5]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[6]",
|
|
"net": "cpu_data_in[6]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe0[7]",
|
|
"net": "cpu_data_in[7]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe1",
|
|
"net": "cpu_rwb",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[0]",
|
|
"net": "cpu_addr[0]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[1]",
|
|
"net": "cpu_addr[1]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[2]",
|
|
"net": "cpu_addr[2]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[3]",
|
|
"net": "cpu_addr[3]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[4]",
|
|
"net": "cpu_addr[4]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[5]",
|
|
"net": "cpu_addr[5]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[6]",
|
|
"net": "cpu_addr[6]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[7]",
|
|
"net": "cpu_addr[7]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[8]",
|
|
"net": "cpu_addr[8]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[9]",
|
|
"net": "cpu_addr[9]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[10]",
|
|
"net": "cpu_addr[10]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[11]",
|
|
"net": "cpu_addr[11]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[12]",
|
|
"net": "cpu_addr[12]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[13]",
|
|
"net": "cpu_addr[13]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[14]",
|
|
"net": "cpu_addr[14]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe2[15]",
|
|
"net": "cpu_addr[15]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe3",
|
|
"net": "cpu_sync",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe4",
|
|
"net": "cpu_rdy",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[0]",
|
|
"net": "w_sdram_addr[0]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[1]",
|
|
"net": "w_sdram_addr[1]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[2]",
|
|
"net": "w_sdram_addr[2]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[3]",
|
|
"net": "w_sdram_addr[3]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[4]",
|
|
"net": "w_sdram_addr[4]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[5]",
|
|
"net": "w_sdram_addr[5]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[6]",
|
|
"net": "w_sdram_addr[6]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[7]",
|
|
"net": "w_sdram_addr[7]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[8]",
|
|
"net": "w_sdram_addr[8]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[9]",
|
|
"net": "w_sdram_addr[9]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[10]",
|
|
"net": "w_sdram_addr[10]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[11]",
|
|
"net": "w_sdram_addr[11]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[12]",
|
|
"net": "w_sdram_addr[12]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[13]",
|
|
"net": "w_sdram_addr[13]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[14]",
|
|
"net": "w_sdram_addr[14]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[15]",
|
|
"net": "w_sdram_addr[15]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[16]",
|
|
"net": "w_sdram_addr[16]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[17]",
|
|
"net": "w_sdram_addr[17]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[18]",
|
|
"net": "w_sdram_addr[18]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[19]",
|
|
"net": "w_sdram_addr[19]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[20]",
|
|
"net": "w_sdram_addr[20]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[21]",
|
|
"net": "w_sdram_addr[21]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[22]",
|
|
"net": "w_sdram_addr[22]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[23]",
|
|
"net": "w_sdram_addr[23]",
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "la0_probe5[24]",
|
|
"net": "w_sdram_addr[24]",
|
|
"path": []
|
|
}
|
|
]
|
|
}
|
|
}
|
|
],
|
|
"vdbs": [
|
|
{
|
|
"file": "debug_top.post.vdb",
|
|
"instance": "edb_top_inst"
|
|
}
|
|
],
|
|
"session": {
|
|
"wizard": {
|
|
"data_depth": 8192,
|
|
"capture_control": false,
|
|
"selected_nets": [
|
|
{
|
|
"name": "cpu_data_in",
|
|
"width": 8,
|
|
"clk_domain": "clk_2",
|
|
"selected_probe_type": "DATA AND TRIGGER",
|
|
"child": [],
|
|
"path": [],
|
|
"net_idx_left": 7,
|
|
"net_idx_right": 0
|
|
},
|
|
{
|
|
"name": "cpu_rwb",
|
|
"width": 1,
|
|
"clk_domain": "clk_2",
|
|
"selected_probe_type": "DATA AND TRIGGER",
|
|
"child": [],
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "cpu_addr",
|
|
"width": 16,
|
|
"clk_domain": "clk_2",
|
|
"selected_probe_type": "DATA AND TRIGGER",
|
|
"child": [],
|
|
"path": [],
|
|
"net_idx_left": 15,
|
|
"net_idx_right": 0
|
|
},
|
|
{
|
|
"name": "cpu_sync",
|
|
"width": 1,
|
|
"clk_domain": "clk_2",
|
|
"selected_probe_type": "DATA AND TRIGGER",
|
|
"child": [],
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "cpu_rdy",
|
|
"width": 1,
|
|
"clk_domain": "clk_2",
|
|
"selected_probe_type": "DATA AND TRIGGER",
|
|
"child": [],
|
|
"path": []
|
|
},
|
|
{
|
|
"name": "w_sdram_addr",
|
|
"width": 25,
|
|
"clk_domain": "clk_2",
|
|
"selected_probe_type": "DATA AND TRIGGER",
|
|
"child": [],
|
|
"path": [],
|
|
"net_idx_left": 24,
|
|
"net_idx_right": 0
|
|
}
|
|
],
|
|
"top_module": "super6502",
|
|
"db_checksum": "ba5fce12098a2c03e7bae2e9a172d1842464edfca8e284870b3519e987537970",
|
|
"src": "elaborate",
|
|
"jtag_user": "USER1",
|
|
"input_pipeline": 1
|
|
}
|
|
}
|
|
} |