25 lines
753 B
Systemverilog
25 lines
753 B
Systemverilog
module addr_decode(
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input logic [23:0] addr,
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output logic sdram_cs,
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output logic rom_cs,
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output logic hex_cs,
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output logic uart_cs,
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output logic irq_cs,
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output logic board_io_cs,
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output logic mm_cs1,
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output logic mm_cs2,
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output logic sd_cs
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);
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assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
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assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
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assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
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assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
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assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
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assign board_io_cs = addr == 24'h007ff6;
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assign mm_cs2 = addr == 24'h007ff7;
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assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffe;
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assign irq_cs = addr == 24'h007fff;
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endmodule
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