44 lines
654 B
Systemverilog
44 lines
654 B
Systemverilog
module bb_spi_controller(
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input clk,
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input rst,
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input spi_cs,
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input logic [7:0] data_in,
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output logic [7:0] data_out,
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input rw,
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output logic SPI_SSn,
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output logic SPI_MOSI,
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output logic SPI_SCLK,
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input SPI_MISO,
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input SPI_slave_IRQ
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);
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logic [7:0] val;
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assign data_out = val;
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assign SPI_SCLK = val[0];
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assign SPI_SSn = val[1];
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assign SPI_MOSI = val[2];
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always @(posedge clk) begin
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if (rst) begin
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val <= 8'h2; //start with SS high
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end
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if (spi_cs & ~rw)
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val <= data_in;
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val[3] <= SPI_MISO;
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val[4] <= SPI_slave_IRQ;
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end
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endmodule
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