Files
super6502/hw/fpga/cpu_clk.qip
2022-03-11 18:25:55 -06:00

6 lines
338 B
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cpu_clk.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cpu_clk.ppf"]