be497ecaa9
Upon reset the memory mapper is automatically disabled, but the mappings are not cleared.
59 lines
1.0 KiB
Systemverilog
59 lines
1.0 KiB
Systemverilog
/*
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* This is based off of the 74LS610, but is not identical.
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Some of the inputs are flipped so that they are all active high,
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and some outputs are reordered.
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Notably, when MM is low, MA is present on MO0-MO4, not 8 to 11.
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*/
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module memory_mapper(
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input clk,
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input rst,
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input rw,
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input cs,
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input MM_cs,
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input [3:0] RS,
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input [3:0] MA,
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input logic [11:0] data_in,
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output logic [11:0] data_out,
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output logic [11:0] MO
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);
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logic [11:0] RAM [16];
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logic MM;
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always_ff @(posedge clk) begin
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if (rst) begin
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MM <= '0;
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end else begin
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if (MM_cs & ~rw) begin // can't read MM but do you really need too?
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MM = |data_in;
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end
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if (cs & ~rw) begin // write to registers
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RAM[RS] <= data_in;
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end else if (cs & rw) begin // read registers
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data_out <= RAM[RS];
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end
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end
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end
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always_comb begin
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if (MM) begin // normal mode
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MO = RAM[MA];
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end else begin // passthrough mode
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MO = {8'b0, MA};
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end
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end
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endmodule
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