39 lines
865 B
Systemverilog
39 lines
865 B
Systemverilog
`timescale 1ns/1ps
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module interrupt_controller_code_tb();
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sim_top u_sim_top();
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always begin
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if (
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u_sim_top.w_cpu_addr == 16'h0 &&
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u_sim_top.w_cpu_we == '1
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) begin
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if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
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$display("Good finish!");
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$finish();
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end else begin
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$display("Bad finish!");
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$finish_and_return(-1);
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end
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end
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# 1;
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end
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initial begin
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u_sim_top.u_dut.int_in = 0;
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repeat (2400) @(posedge u_sim_top.r_clk_cpu);
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for (int i = 0; i < 256; i++) begin
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repeat (100) @(posedge u_sim_top.r_clk_cpu);
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u_sim_top.u_dut.int_in = 1 << i;
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$display("Activiating interrupt %d", i);
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end
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end
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initial begin
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repeat (40000) @(posedge u_sim_top.r_clk_cpu);
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$display("Timed out");
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$finish_and_return(-1);
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end
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endmodule |