194c4b456f
Based on the 74ls610 but with some slight changes. The memory mapper works by having a 16x12 ram array. The top 4 bits of the address are used to index into this array, and the resulting word replaces those top 4 bits. In this way, a 16 bit address is replaced with a 24 bit address. As of now there is no way to write 12 bit values though, so currently we are using 20 bit addresses. There is a chip select line that allows you to write into the ram array, and another chip select that allows you to write to the control word. Currently the control word is just a single bit, the enable bit. When not enabled, the 4 index bits are passed straight through, and the higher bits of the address are replaced with 0, a sort of identity map. Once enabled, it operates as described above. Since the bottom 12 bits are left unchanged, the page size is 4kb. There are no protections so far, but might be added later, as well as the ability to actually use all 12 bits.
54 lines
894 B
Systemverilog
54 lines
894 B
Systemverilog
/*
|
|
* This is based off of the 74LS610, but is not identical.
|
|
Some of the inputs are flipped so that they are all active high,
|
|
and some outputs are reordered.
|
|
Notably, when MM is low, MA is present on MO0-MO4, not 8 to 11.
|
|
*/
|
|
|
|
module memory_mapper(
|
|
input clk,
|
|
|
|
input rw,
|
|
input cs,
|
|
|
|
input MM_cs,
|
|
|
|
input [3:0] RS,
|
|
|
|
input [3:0] MA,
|
|
|
|
input logic [11:0] data_in,
|
|
output logic [11:0] data_out,
|
|
|
|
output logic [11:0] MO
|
|
);
|
|
|
|
logic [11:0] RAM [16];
|
|
|
|
logic MM;
|
|
|
|
|
|
always_ff @(posedge clk) begin
|
|
if (MM_cs & ~rw) begin // can't read MM but do you really need too?
|
|
MM = |data_in;
|
|
end
|
|
|
|
if (cs & ~rw) begin // write to registers
|
|
RAM[RS] <= data_in;
|
|
end else if (cs & rw) begin // read registers
|
|
data_out <= RAM[RS];
|
|
end
|
|
end
|
|
|
|
|
|
always_comb begin
|
|
if (MM) begin // normal mode
|
|
MO = RAM[MA];
|
|
end else begin // passthrough mode
|
|
MO = {8'b0, MA};
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|