Files
super6502/hw/efinix_fpga/ip/divider/divider_tmpl.vhd
Byron Lathi 21e3a477c1 Update IP
2023-07-19 21:06:20 -07:00

65 lines
3.3 KiB
VHDL

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-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
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-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
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--
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------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT divider is
PORT (
numer : in std_logic_vector(15 downto 0);
denom : in std_logic_vector(15 downto 0);
clken : in std_logic;
clk : in std_logic;
reset : in std_logic;
quotient : out std_logic_vector(15 downto 0);
remain : out std_logic_vector(15 downto 0);
rfd : out std_logic);
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_divider : divider
PORT MAP (
numer => numer,
denom => denom,
clken => clken,
clk => clk,
reset => reset,
quotient => quotient,
remain => remain,
rfd => rfd);
------------------------ End INSTANTIATION Template ---------