5d8c4aab44
Adds the usb code that we got in ECE 385. It will not work now, and parts that involve the timer are disabled. It does compile though, with a few warnings. The goal will be to add USB MSD support, which is not actually given to us so I will have to do myself or find some other code to base it off of.
251 lines
8.5 KiB
C
251 lines
8.5 KiB
C
//Fill in your low-level SPI functions here, as per your host platform
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#define _MAX3421E_C_
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include "project_config.h"
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#include <spi.h>
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#include <gpio.h>
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#include <unistd.h>
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//variables and data structures
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//External variables
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extern BYTE usb_task_state;
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uint8_t* usb_gpio = USB_GPIO;
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/* Functions */
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void SPI_init(BYTE sync_mode, BYTE bus_mode, BYTE smp_phase) {
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//Don't need to initialize SPI port, already ready to go with BSP
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(void) sync_mode;
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(void) bus_mode;
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(void) smp_phase;
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}
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//writes single byte to MAX3421E via SPI, simultanously reads status register and returns it
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BYTE SPI_wr(BYTE data) {
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(void) data;
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//This function is never used by the code, so you do not need to fill it in
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return -1;
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}
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//writes register to MAX3421E via SPI
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void MAXreg_wr(BYTE reg, BYTE val) {
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//psuedocode:
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//select MAX3421E (may not be necessary if you are using SPI peripheral)
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//write reg + 2 via SPI
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//write val via SPI
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//read return code from SPI peripheral (see Intel documentation)
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//if return code < 0 print an error
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//deselect MAX3421E (may not be necessary if you are using SPI peripheral)
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BYTE regdir = reg + 2; //reg bitshift plus direction bit.
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spi_byte(regdir);
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spi_byte(val);
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spi_deselect();
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}
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//multiple-byte write
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//returns a pointer to a memory position after last written
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BYTE* MAXbytes_wr(BYTE reg, BYTE nbytes, BYTE* data) {
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//psuedocode:
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//select MAX3421E (may not be necessary if you are using SPI peripheral)
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//write reg + 2 via SPI
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//write data[n] via SPI, where n goes from 0 to nbytes-1
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//read return code from SPI peripheral (see Intel documentation)
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//if return code < 0 print an error
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//deselect MAX3421E (may not be necessary if you are using SPI peripheral)
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//return (data + nbytes);
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int i;
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BYTE regdir = reg + 2;
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spi_byte(regdir);
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for (i = 0; i < nbytes; i++){
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spi_byte(data[i]);
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}
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spi_deselect();
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return data + nbytes;
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}
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//reads register from MAX3421E via SPI
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BYTE MAXreg_rd(BYTE reg) {
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//psuedocode:
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//select MAX3421E (may not be necessary if you are using SPI peripheral)
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//write reg via SPI
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//read val via SPI
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//read return code from SPI peripheral (see Intel documentation)
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//if return code < 0 print an error
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//deselect MAX3421E (may not be necessary if you are using SPI peripheral)
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//return val
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BYTE regdir = reg;
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BYTE rxdata;
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spi_byte(regdir);
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rxdata = spi_byte(0);
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spi_deselect();
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return rxdata;
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}
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//multiple-byte write
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//returns a pointer to a memory position after last written
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BYTE* MAXbytes_rd(BYTE reg, BYTE nbytes, BYTE* data) {
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//psuedocode:
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//select MAX3421E (may not be necessary if you are using SPI peripheral)
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//write reg via SPI
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//read data[n] from SPI, where n goes from 0 to nbytes-1
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//read return code from SPI peripheral (see Intel documentation)
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//if return code < 0 print an error
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//deselect MAX3421E (may not be necessary if you are using SPI peripheral)
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//return (data + nbytes);
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int i;
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BYTE regdir = reg;
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spi_byte(regdir);
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for (i = 0; i < nbytes; i++){
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data[i] = spi_byte(0);
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}
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spi_deselect();
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return data + nbytes;
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}
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/* reset MAX3421E using chip reset bit. SPI configuration is not affected */
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void MAX3421E_reset(void) {
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//hardware reset, then software reset
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BYTE tmp;
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*usb_gpio &= ~USB_GPIO_RST;
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//TODO
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//sleep(1);
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*usb_gpio |= USB_GPIO_RST;
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tmp = 0;
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MAXreg_wr( rUSBCTL, bmCHIPRES); //Chip reset. This stops the oscillator
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MAXreg_wr( rUSBCTL, 0x00); //Remove the reset
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while (!(MAXreg_rd( rUSBIRQ) & bmOSCOKIRQ)) { //wait until the PLL stabilizes
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tmp++; //timeout after 256 attempts
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if (tmp == 0) {
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//printf("reset timeout!");
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}
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}
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}
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/* turn USB power on/off */
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/* ON pin of VBUS switch (MAX4793 or similar) is connected to GPOUT7 */
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/* OVERLOAD pin of Vbus switch is connected to GPIN7 */
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/* OVERLOAD state low. NO OVERLOAD or VBUS OFF state high. */
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BOOL Vbus_power(BOOL action) {
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// power on/off successful
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return (1);
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}
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/* probe bus to determine device presense and speed */
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void MAX_busprobe(void) {
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BYTE bus_sample;
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// MAXreg_wr(rHCTL,bmSAMPLEBUS);
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bus_sample = MAXreg_rd( rHRSL); //Get J,K status
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bus_sample &= ( bmJSTATUS | bmKSTATUS); //zero the rest of the byte
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switch (bus_sample) { //start full-speed or low-speed host
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case ( bmJSTATUS):
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/*kludgy*/
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if (usb_task_state != USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE) { //bus reset causes connection detect interrupt
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if (!(MAXreg_rd( rMODE) & bmLOWSPEED)) {
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MAXreg_wr( rMODE, MODE_FS_HOST); //start full-speed host
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//printf("Starting in full speed\n");
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} else {
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MAXreg_wr( rMODE, MODE_LS_HOST); //start low-speed host
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//printf("Starting in low speed\n");
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}
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usb_task_state = ( USB_STATE_ATTACHED); //signal usb state machine to start attachment sequence
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}
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break;
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case ( bmKSTATUS):
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if (usb_task_state != USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE) { //bus reset causes connection detect interrupt
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if (!(MAXreg_rd( rMODE) & bmLOWSPEED)) {
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MAXreg_wr( rMODE, MODE_LS_HOST); //start low-speed host
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//printf("Starting in low speed\n");
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} else {
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MAXreg_wr( rMODE, MODE_FS_HOST); //start full-speed host
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//printf("Starting in full speed\n");
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}
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usb_task_state = ( USB_STATE_ATTACHED); //signal usb state machine to start attachment sequence
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}
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break;
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case ( bmSE1): //illegal state
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usb_task_state = ( USB_DETACHED_SUBSTATE_ILLEGAL);
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break;
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case ( bmSE0): //disconnected state
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if (!((usb_task_state & USB_STATE_MASK) == USB_STATE_DETACHED)) //if we came here from other than detached state
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usb_task_state = ( USB_DETACHED_SUBSTATE_INITIALIZE); //clear device data structures
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else {
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MAXreg_wr( rMODE, MODE_FS_HOST); //start full-speed host
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usb_task_state = ( USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE);
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}
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break;
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} //end switch( bus_sample )
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}
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/* MAX3421E initialization after power-on */
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void MAX3421E_init(void) {
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/* Configure full-duplex SPI, interrupt pulse */
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MAXreg_wr( rPINCTL, (bmFDUPSPI + bmINTLEVEL + bmGPXB)); //Full-duplex SPI, level interrupt, GPX
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MAX3421E_reset(); //stop/start the oscillator
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/* configure power switch */
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Vbus_power( OFF); //turn Vbus power off
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MAXreg_wr( rGPINIEN, bmGPINIEN7); //enable interrupt on GPIN7 (power switch overload flag)
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Vbus_power( ON);
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/* configure host operation */
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MAXreg_wr( rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST | bmSEPIRQ); // set pull-downs, SOF, Host, Separate GPIN IRQ on GPX
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//MAXreg_wr( rHIEN, bmFRAMEIE|bmCONDETIE|bmBUSEVENTIE ); // enable SOF, connection detection, bus event IRQs
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MAXreg_wr( rHIEN, bmCONDETIE); //connection detection
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/* HXFRDNIRQ is checked in Dispatch packet function */
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MAXreg_wr(rHCTL, bmSAMPLEBUS); // update the JSTATUS and KSTATUS bits
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MAX_busprobe(); //check if anything is connected
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MAXreg_wr( rHIRQ, bmCONDETIRQ); //clear connection detect interrupt
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MAXreg_wr( rCPUCTL, 0x01); //enable interrupt pin
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}
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/* MAX3421 state change task and interrupt handler */
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void MAX3421E_Task(void) {
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if ((*usb_gpio & USB_GPIO_IRQ) == 0) {
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//printf("MAX interrupt\n\r");
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MaxIntHandler();
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}
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if ((*usb_gpio & USB_GPIO_GPX) != 0) {
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//printf("GPX interrupt\n\r");
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MaxGpxHandler();
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}
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}
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void MaxIntHandler(void) {
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BYTE HIRQ;
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BYTE HIRQ_sendback = 0x00;
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HIRQ = MAXreg_rd( rHIRQ); //determine interrupt source
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//printf("IRQ: %x\n", HIRQ);
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if (HIRQ & bmFRAMEIRQ) { //->1ms SOF interrupt handler
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HIRQ_sendback |= bmFRAMEIRQ;
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} //end FRAMEIRQ handling
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if (HIRQ & bmCONDETIRQ) {
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MAX_busprobe();
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HIRQ_sendback |= bmCONDETIRQ; //set sendback to 1 to clear register
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}
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if (HIRQ & bmSNDBAVIRQ) //if the send buffer is clear (previous transfer completed without issue)
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{
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MAXreg_wr(rSNDBC, 0x00);//clear the send buffer (not really necessary, but clears interrupt)
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}
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if (HIRQ & bmBUSEVENTIRQ) { //bus event is either reset or suspend
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usb_task_state++; //advance USB task state machine
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HIRQ_sendback |= bmBUSEVENTIRQ;
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}
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/* End HIRQ interrupts handling, clear serviced IRQs */
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MAXreg_wr( rHIRQ, HIRQ_sendback); //write '1' to CONDETIRQ to ack bus state change
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}
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void MaxGpxHandler(void) {
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BYTE GPINIRQ;
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GPINIRQ = MAXreg_rd( rGPINIRQ); //read both IRQ registers
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}
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