15 lines
271 B
Systemverilog
15 lines
271 B
Systemverilog
`timescale 1ns/1ps
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module uart_irq_tb();
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sim_top u_sim_top();
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initial begin
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u_sim_top.u_sim_uart.tx_en = 1;
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@(posedge u_sim_top.r_clk_cpu);
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u_sim_top.u_sim_uart.tx_data = 8'hAA;
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repeat (100) @(posedge u_sim_top.r_clk_cpu);
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$finish();
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end
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endmodule |