31 lines
704 B
Systemverilog
31 lines
704 B
Systemverilog
module byte_sel_register
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#(
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parameter DATA_WIDTH = 8,
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parameter ADDR_WIDTH = 32
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)(
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input i_clk,
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input i_reset,
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input i_write,
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input [$clog2(ADDR_WIDTH)-1:0] i_byte_sel,
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input [DATA_WIDTH-1:0] i_data,
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output [DATA_WIDTH-1:0] o_data,
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output [DATA_WIDTH*ADDR_WIDTH-1:0] o_full_data
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);
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logic [DATA_WIDTH*ADDR_WIDTH-1:0] r_data;
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assign o_data = r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH];
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assign o_full_data = r_data;
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always_ff @(posedge i_clk) begin
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if (i_reset) begin
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r_data <= '0;
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end else begin
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r_data <= r_data;
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if (i_write) begin
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r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH] <= i_data;
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end
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end
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end
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endmodule |