67 lines
1.2 KiB
Systemverilog
67 lines
1.2 KiB
Systemverilog
module mapper(
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input i_reset,
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input i_clk,
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input i_clk50,
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input i_clk100,
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input i_cs,
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input i_we,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input [15:0] i_cpu_addr,
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output logic [24:0] o_mapped_addr
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);
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logic [15:0] mm [16];
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logic [15:0] _mm [16];
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logic [15:0] mm_next [16];
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logic [31:0] we;
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// TODO These have basically the same name.
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logic [15:0] mm_sel;
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logic [15:0] selected_mm;
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logic [15:0] _cpu_addr;
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always_comb begin
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we = ((i_we & i_cs) << i_cpu_addr[4:0]);
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mm_sel = (1 << i_cpu_addr[4:1]);
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o_data = mm_sel[8*i_cpu_addr[0] +: 8];
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o_mapped_addr = {selected_mm[12:0], i_cpu_addr[11:0]};
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for (int i = 0; i < 16; i++) begin
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mm_next[i] = mm[i];
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end
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for (int i = 0; i < 32; i++) begin
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if (we[i]) begin
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mm_next[i/2][(i%2)*8 +: 8] = i_data;
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end
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end
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end
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always_ff @(posedge i_clk100) begin
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_cpu_addr <= i_cpu_addr;
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selected_mm <= mm[_cpu_addr[15:12]];
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end
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always_ff @(negedge i_clk or posedge i_reset) begin
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if (i_reset) begin
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for (int i = 0; i < 16; i++) begin
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mm[i] <= i;
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end
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end else begin
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for (int i = 0; i < 16; i++) begin
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mm[i] <= mm_next[i];
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end
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end
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end
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endmodule
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