170 lines
3.7 KiB
Systemverilog
170 lines
3.7 KiB
Systemverilog
module rtc(
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input clk,
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input reset,
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input rwb,
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input cs,
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input addr,
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input [7:0] i_data,
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output logic [7:0] o_data,
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output logic irq
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);
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localparam REG_SIZ = 32;
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logic [REG_SIZ-1:0] r_counter, r_counter_next;
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logic [REG_SIZ-1:0] r_irq_counter, r_irq_counter_next;
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// Because we need to increment this, it can't be
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// a byte sel register. Thats fine because we don't need
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// to be able to write from the cpu anyway.
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logic [REG_SIZ-1:0] r_output, r_output_next;
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logic [1:0] w_byte_sel;
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logic w_increment_write;
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logic [7:0] w_increment_data;
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logic [REG_SIZ-1:0] w_increment_full_data;
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byte_sel_register #(
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.DATA_WIDTH(8),
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.ADDR_WIDTH(REG_SIZ/8)
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) u_increment_reg (
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.i_clk(~clk),
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.i_reset(reset),
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.i_write(w_increment_write),
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.i_byte_sel(w_byte_sel),
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.i_data(i_data),
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.o_data(w_increment_data),
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.o_full_data(w_increment_full_data)
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);
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logic w_threshold_write;
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logic [7:0] w_threshold_data;
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logic [REG_SIZ-1:0] w_threshold_full_data;
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byte_sel_register #(
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.DATA_WIDTH(8),
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.ADDR_WIDTH(REG_SIZ/8)
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) u_threshold_reg (
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.i_clk(~clk),
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.i_reset(reset),
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.i_write(w_threshold_write),
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.i_byte_sel(w_byte_sel),
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.i_data(i_data),
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.o_data(w_threshold_data),
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.o_full_data(w_threshold_full_data)
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);
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logic w_irq_threshold_write;
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logic [7:0] w_irq_threshold_data;
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logic [REG_SIZ-1:0] w_irq_threshold_full_data;
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byte_sel_register #(
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.DATA_WIDTH(8),
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.ADDR_WIDTH(REG_SIZ/8)
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) u_irq_threshold_reg (
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.i_clk(~clk),
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.i_reset(reset),
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.i_write(w_irq_threshold_write),
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.i_byte_sel(w_byte_sel),
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.i_data(i_data),
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.o_data(w_irq_threshold_data),
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.o_full_data(w_irq_threshold_full_data)
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);
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logic we, re;
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assign we = cs & ~rwb;
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assign re = cs & rwb;
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logic [7:0] cmd, cmd_next;
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logic [7:0] ctrl, ctrl_next;
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always_comb begin
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if (addr == '0 && we) begin
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cmd_next = i_data;
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end else begin
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cmd_next = cmd;
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end
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w_increment_write = 0;
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w_threshold_write = 0;
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w_irq_threshold_write = 0;
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w_byte_sel = cmd[3:0];
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ctrl_next = ctrl;
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if (addr == '1) begin
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unique casez (cmd)
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8'h0?: begin
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w_threshold_write = we;
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o_data = w_threshold_data;
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end
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8'h1?: begin
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w_increment_write = we;
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o_data = w_increment_data;
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end
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8'h2?: begin
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w_irq_threshold_write = we;
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o_data = w_irq_threshold_data;
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end
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8'h3?: begin
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if (we) begin
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ctrl_next = i_data;
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end
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o_data = r_output[8*w_byte_sel +: 8];
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end
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endcase
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end
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end
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always_comb begin
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r_counter_next = r_counter + w_increment_full_data;
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r_irq_counter_next = r_irq_counter;
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r_output_next = r_output;
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if (r_counter == w_threshold_full_data) begin
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r_counter_next = '0;
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r_irq_counter_next = r_irq_counter + 1;
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r_output_next = r_output + 1;
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end
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irq = 0;
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if (r_irq_counter == w_irq_threshold_full_data) begin
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irq = ctrl[1];
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r_irq_counter_next = '0;
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end
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if (ctrl[0] == '0) begin
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r_irq_counter_next = 0;
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r_counter_next = '0;
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r_output_next = '0;
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end
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end
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// Does it matter if we do negedge clock or just invert the input to the module?
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always_ff @(negedge clk) begin
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if (reset) begin
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r_counter <= '0;
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r_irq_counter <= '0;
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r_output <= '0;
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cmd <= '0;
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ctrl <= '0;
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end else begin
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ctrl <= ctrl_next;
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cmd <= cmd_next;
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r_counter <= r_counter_next;
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r_irq_counter <= r_irq_counter_next;
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r_output <= r_output_next;
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end
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end
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endmodule |